Graphics command parsing mechanism
A mechanism for command stream processing is described. A method of embodiments, as described herein, includes fetching cache lines from a memory to fill command first in first out buffer (FIFO), wherein the fetched cachelines an overfetching of data necessary to process a command, a first parser to fetch and execute batch commands stored in the command FIFO and a second parser to fetch commands and execute the batch commands and non-batch commands stored in the command FIFO.
1. An apparatus to facilitate command parsing, comprising:
a direct memory access (DMA) fetch to provide one or more addresses to fetch commands from memory;
a command first in first out buffer (FIFO) to store the fetched commands and track addresses that have been fetched;
a first parser to fetch and execute batch commands stored in the command FIFO, the command FIFO further operable to store non-batch commands; and
a second parser to fetch non-batch commands and execute the batch commands and non-batch commands stored in the command FIFO,
wherein the first parser locates an occurrence of a buffer switch point and fetches a corresponding instruction to the located occurrence and stores it in the command FIFO prior to the second parser reaching the instruction.
2. The apparatus of claim 1 , wherein the first parser and the second parser parse cachelines of data upon receipt in the command FIFO.
3. The apparatus of claim 1 , wherein the second parser notifies the DMA fetch to restart at a new address whenever the first parser parses a command that requires a different buffer to be fetched.
4. The apparatus of claim 3 , wherein the DMA fetch fetches updated cachelines corresponding to the new address and the command FIFO replaces overfetched data with the updated cachelines.
5. The apparatus of claim 1 , wherein the first parser is programmable to support branching based on predication.
6. The apparatus of claim 5 , wherein the first parser is programmed to always branch.
7. The apparatus of claim 5 , wherein the first parser is programmed to always continue.
8. A method to facilitate command parsing, comprising:
fetching cache lines from a memory to fill command first in first out buffer (FIFO);
a first parser fetching batch commands stored in the command FIFO, the command FIFO further operable to store non-batch commands;
the first parser executing the batch commands;
a second parser fetching non-batch commands stored in the command FIFO; and
the second parser executing the batch commands and non-batch commands stored in the command FIFO,
wherein the first parser locates an occurrence of a buffer switch point and fetches a corresponding instruction to the located occurrence and stores it in the command FIFO prior to the second parser reaching the instruction.
9. The method of claim 8 , further comprising: the second parser notifying a direct memory access (DMA) fetch to start a new address whenever the first parser parses a command that requires a different buffer to be fetched; and the DMA fetch fetching updated cachelines corresponding to the new address.
10. The method of claim 9 , further comprising replacing overfetched data in the command FIFO with the updated cachelines.
11. The method of claim 8 , wherein the first parser is programmable to support branching based on predication.
12. A graphics processing unit (GPU) comprising a command streamer, including:
a direct memory access (DMA) fetch to provide one or more addresses to fetch commands from memory;
a command first in first out buffer (FIFO) to store the fetched commands and track addresses that have been fetched;
a first parser to fetch and execute batch commands stored in the command FIFO, the command FIFO is further operable to store non-batch commands; and
a second parser to fetch non-batch commands and execute the batch commands and non-batch commands stored in the command FIFO,
wherein the first parser locates an occurrence of a buffer switch point and fetches a corresponding instruction to the located occurrence and stores it in the command FIFO prior to the second parser reaching the instruction.
13. The GPU of claim 12 , wherein the second parser notifies the DMA fetch to restart at a new address whenever the first parser parses a command that requires a different buffer to be fetched.
14. The GPU of claim 13 , wherein the DMA fetch fetches updated cachelines corresponding to the new address and the command FIFO replaces overfetched data with the updated cachelines.
15. The GPU of claim 12 , wherein the first parser is programmable to support branching based on predication.
16. The GPU of claim 15 , wherein the first parser is programmed to always branch.
17. The GPU of claim 15 , wherein the first parser is programmed to always continue.
18. The GPU of claim 17 , wherein the command streamer tracks data writes from the second parser that match with addresses in the command FIFO.
19. The GPU of claim 18 , wherein a corresponding entry in the command FIFO is updated upon a determination that there is a match between data writes from the second parser and addresses in the command FIFO.
20. A system to facilitate command parsing, comprising:
a memory; and
a command streamer, including:
a direct memory access (DMA) fetch to provide one or more addresses to fetch commands from the memory;
a command first in first out buffer (FIFO) to store the fetched commands and track addresses that have been fetched;
a first parser to fetch and execute batch commands stored in the command FIFO, the command FIFO is further operable to store non-batch commands; and
a second parser to fetch non-batch commands and execute the batch commands and non-batch commands stored in the command FIFO,
wherein the first parser locates an occurrence of a buffer switch point and fetches a corresponding instruction in the command FIFO prior to the second parser reaching the instruction.