Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro

1. A hard macro having a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro from the top to the bottom and including an array of blockage sites extending through the hard macro, wherein the plurality of vias are formed in at least some of the array of blockage sites and wherein at least one via is configured to connect a first element to a second element, the first element in a first layer different from a layer that includes the hard macro, the first element positioned in a first direction from a line that passes through the at least one via, the second element in a second layer different from the layer that includes the hard macro, the second element positioned in a second direction from the line that passes through the at least one via, and wherein, between the top and the bottom of the hard macro, the line is entirely contained within the hard macro.

2. The hard macro of claim 1 , wherein the blockage sites in the array of blockage sites have a consistent spacing therebetween.

3. The hard macro of claim 1 , integrated into at least one semiconductor die.

4. The hard macro of claim 1 , integrated into a device, selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, or a computer.

5. The hard macro of claim 1 , wherein the blockage sites in the array of blockage sites extend linearly from the top to the bottom.

6. The hard macro of claim 1 , wherein the blockage sites in the array of blockage sites are arranged in rows and columns on the top of the hard macro, and wherein:

the rows have a constant spacing; or

the rows and the columns have a constant spacing.

7. The hard macro of claim 1 , wherein the blockage sites in the array of blockage sites are arranged in at least two rows and at least two columns.

8. The hard macro of claim 1 , wherein the blockage sites in the array of blockage sites are arranged in a zig-zag pattern.

9. The hard macro of claim 1 , wherein the blockage sites in the array of blockage sites are arranged in an irregular pattern.

10. A non-volatile computer readable medium storing instructions configured to cause a computer-controlled device to create a hard macro having:

a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom,

a plurality of vias extending through the hard macro from the top to the bottom, and

an array of blockage sites extending through the hard macro, wherein the plurality of vias are formed in at least some of the array of blockage sites and wherein at least one via is configured to connect a first element to a second element, the first element in a first layer different from a layer that includes the hard macro, the first element positioned in a first direction from a line that passes through the at least one via, the second element in a second layer different from the layer that includes the hard macro, the second element positioned in a second direction from the line that passes through the at least one via, and wherein, between the top and the bottom of the hard macro, the line is entirely contained within the hard macro.

11. An integrated circuit, comprising: a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the at least one middle layer including a hard macro having an array of blockage sites extending through the hard macro between a top and a bottom of the hard macro, and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through a blockage site in the array of blockage sites and wherein the via is configured to connect a first element to a second element, the first element in the top layer, the first element positioned in a first direction from a line that passes through the via, the second element in the bottom layer, the second element positioned in a second direction from the line that passes through the via, and wherein, between the top and the bottom of the hard macro, the line is entirely contained within the hard macro.

12. The integrated circuit of claim 11 , integrated into at least one semiconductor die.

13. The integrated circuit of claim 11 , integrated into a device, selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, or a computer.

14. A non-volatile computer readable medium storing instructions configured cause a computer-controlled device to create an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the at least one middle layer including a hard macro having an array of blockage sites extending through the hard macro between a top and a bottom of the hard macro, and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through a blockage site in the array of blockage sites and wherein the via is configured to connect a first element to a second element, the first element in the top layer, the first element positioned in a first direction from a line that passes through the via, the second element in the bottom layer, the second element positioned in a second direction from the line that passes through the via, and wherein, between the top and the bottom of the hard macro, the line is entirely contained within the hard macro.

15. A hard macro having a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including:

an array of blockage means for enabling via formation through the hard macro; and

a via in the array of blockage means, wherein the via is configured to connect a first element to a second element, the first element in a first layer different from a layer that includes the hard macro, the first element positioned in a first direction from a line that passes through the via, the second element in a second layer different from the layer that includes the hard macro, the second element positioned in a second direction from the line that passes through the via, and wherein, between the top and the bottom of the hard macro, the line is entirely contained within the hard macro.

16. The hard macro of claim 15 , integrated into at least one semiconductor die.

17. The hard macro of claim 15 , integrated into a device, selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, or a computer.