IP Library Granted Patent US 10,192,815
Granted Patent B2
US 10,192,815 · App. 15/441,559 · Granted Jan 29, 2019

Wiring board and semiconductor device

Inventors: Kosuke Tsukamoto (Nagano, JP); Noriyoshi Shimizu (Nagano, JP)
Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
H01L23/49838H01L21/486H01L21/4853H01L21/4857H01L23/3121H01L23/49822H01L23/49827H01L24/17H01L25/0655H01L24/81H01L2224/13014H01L2224/13144H01L2224/16113H01L2224/16168H01L2224/16501H01L2224/81193H01L2224/81815H01L2924/014H01L2924/0105H01L2924/01022H01L2924/01024H01L2924/01028H01L2924/01029H01L2924/01046H01L2924/01047H01L2924/01073H01L2924/01079H01L2924/04941H01L2924/04953H01L2924/05432H01L2924/05442H01L2924/07025H01L2924/1432H01L2924/1436H01L2924/1437H01L2924/1438H01L2924/1579H01L2924/15747H01L2924/15787
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,192,815
App. No.
15/441,559
Granted
Jan 29, 2019
Kind
B2
Abstract

A wiring board includes: a first insulating layer; a first wiring layer formed on a lower surface of the first insulating layer; a first through hole which penetrates the first insulating layer; a first via wiring including: a filling portion formed to fill the first through hole; and a protruding portion protruding upward from an upper surface of the first insulating layer; a second wiring layer including a land, wherein the land includes an outer circumferential portion and a central portion, a second insulating layer formed on the upper surface of the first insulating layer; a second through hole which penetrates the second insulating layer in the thickness direction; a second via wiring formed to fill the second through hole; and a third wiring layer formed on an upper surface of the second insulating layer.

Claims (39)

1. A wiring board comprising:

a first insulating layer;

a first wiring layer formed on a lower surface of the first insulating layer;

a first through hole which penetrates the first insulating layer in a thickness direction of the first insulating layer;

a first via wiring comprising:

a filling portion formed to fill the first through hole and connected to the first wiring layer; and

a protruding portion protruding upward from an upper surface of the first insulating layer;

a second wiring layer comprising a land, wherein the land comprises:

an outer circumferential portion covering the upper surface of the first insulating layer; and

a central portion formed integrally with the outer circumferential portion to cover a side surface and an upper surface of the protruding portion and protruding upward from an upper surface of the outer circumferential portion,

a second insulating layer formed on the upper surface of the first insulating layer to cover the second wiring layer;

a second through hole which penetrates the second insulating layer in the thickness direction to expose a side surface and an upper surface of the central portion;

a second via wiring formed to fill the second through hole to cover the side surface and the upper surface of the central portion; and

a third wiring layer formed on an upper surface of the second insulating layer and connected to the second via wiring,

wherein

the filling portion comprises:

a first metal film covering an inner side surface of the first through hole, the first metal film including an upper end surface that is planar with the upper surface of the first insulating layer;

a second metal film covering the first metal film; and

a metal layer covering the second metal film,

the protruding portion comprises:

the metal layer protruding upward from the upper surface of the first insulating layer; and

the second metal film covering a side surface and an upper surface of the metal layer exposed from the upper surface of the first insulating layer, and

the first via wiring has a step at a boundary between the protruding portion and the filling portion, the step formed along the upper end surface of the first metal film and a side surface and an upper surface of the second metal film, the side surface and the upper surface of the second metal film being exposed from the first metal film.

2. The wiring board of claim 1 , wherein

the first through hole is formed such that a width of an opening end of the first through hole opposed to the second wiring layer is smaller than a width of an opening end of the first through hole opposed to the first wiring layer, and

the second through hole is formed such that a width of an opening end of the second through hole opposed to the second wiring layer is smaller than a width of an opening end of the second through hole opposed to the third wiring layer.

3. The wiring board of claim 1 , wherein

a thickness of the first insulating layer is greater than that of the second insulating layer.

4. The wiring board of claim 1 , wherein

the second wiring layer comprises:

a metal film covering the upper surface of the first insulating layer and the side surface and the upper surface of the protruding portion; and

a metal layer formed on the metal film.

5. The wiring board of claim 1 , wherein

the second via wiring comprises:

a metal film covering an inner side surface of the second through hole and the side surface and the upper surface of the central portion exposed in the second through hole

a metal layer covering the metal film.

6. A semiconductor device comprising:

the wiring board of claim 1 ; and

an electronic component connected to the third wiring layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2017
From: TSUKAMOTO, KOSUKE; SHIMIZU, NORIYOSHI
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 041371/0059 →
Priority Claims (1)
JP 2016-047204 · Mar 10, 2016 · national
Continuity (1)
Related Publication 20170263545A1 · Sep 14, 2017