IP Library › Granted Patent US 10,192,848
Granted Patent B2
US 10,192,848 · App. 15/712,680 · Granted Jan 29, 2019

Package assembly

Inventors: Hung-Jen Lin (Tainan, TW); Tsung-Ding Wang (Tainan, TW); Chien-Hsiun Lee (Chu-Tung Town, TW); Wen-Hsiung Lu (Jhonghe, TW); Ming-Da Cheng (Jhubei, TW); Chung-Shi Liu (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L24/81H01L21/563H01L21/565H01L21/566H01L21/768H01L23/3114H01L23/3171H01L24/11H01L23/525H01L24/02H01L24/03H01L24/05H01L24/13H01L24/16H01L24/27H01L24/29H01L24/83H01L24/92H01L24/94H01L2224/024H01L2224/0239H01L2224/02311H01L2224/0347H01L2224/0362H01L2224/03612H01L2224/03614H01L2224/0401H01L2224/05008H01L2224/05073H01L2224/05124H01L2224/05147H01L2224/05166H01L2224/05187H01L2224/05582H01L2224/05611H01L2224/05644H01L2224/05647H01L2224/05655H01L2224/05666H01L2224/05681H01L2224/1146H01L2224/11334H01L2224/11849H01L2224/131H01L2224/13022H01L2224/13111H01L2224/13113H01L2224/13116H01L2224/13139H01L2224/13144H01L2224/13147H01L2224/13155H01L2224/16145H01L2224/16225H01L2224/16227H01L2224/21H01L2224/27318H01L2224/27334H01L2224/27416H01L2224/2919H01L2224/73204H01L2224/81024H01L2224/81191H01L2224/81203H01L2224/81801H01L2224/81815H01L2224/83192H01L2224/83855H01L2224/92125H01L2224/94H01L2924/00014H01L2924/01013H01L2924/01047H01L2924/12042H01L2924/181H01L2924/2076
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,192,848
App. No.
15/712,680
Granted
Jan 29, 2019
Kind
B2
Abstract

In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

Claims (37)

1. A package assembly, comprising:

a bump on a first substrate;

a molding compound on the first substrate and contacting sidewalls of the bump;

a no-flow underfill layer on a conductive region of a second substrate, wherein the no-flow underfill layer and the conductive region contact the bump; and

a mask layer arranged on the second substrate and laterally surrounding the no-flow underfill layer, wherein the no-flow underfill layer contacts the second substrate between the conductive region and the mask layer, wherein the no-flow underfill layer physically contacts sidewalls and an upper surface of the mask layer facing the first substrate, and wherein the upper surface of the mask layer continuously extends from directly below the no-flow underfill layer to a non-zero distance laterally past an outermost edge of the no-flow underfill layer.

2. The package assembly of claim 1 , wherein the no-flow underfill layer extends to a first height above the second substrate that is greater than a second height of the mask layer above the second substrate.

3. The package assembly of claim 1 , wherein sidewalls of the bump protrude outward from within the no-flow underfill layer to over the no-flow underfill layer.

4. The package assembly of claim 1 , wherein the bump is laterally separated from the mask layer by the no-flow underfill layer.

5. The package assembly of claim 1 , further comprising:

a contact pad arranged on the first substrate;

a post passivation interconnect layer arranged on the contact pad and separated from the first substrate by a first protective layer;

a second protective layer covering the post passivation interconnect layer; and

an under-bump metallurgy extending through the second protective layer, wherein the under-bump metallurgy contacts the bump and further contacts the post passivation interconnect layer at a position that is offset from the contact pad by a second non-zero distance.

6. The package assembly of claim 1 , wherein the molding compound is entirely above both the mask layer and the no-flow underfill layer.

7. The package assembly of claim 1 , wherein a top surface of the no-flow underfill layer facing the molding compound is below a bottom surface of the molding compound facing the no-flow underfill layer.

8. The package assembly of claim 1 , wherein the no-flow underfill layer contacts vertical and horizontal surfaces of the mask layer.

9. The package assembly of claim 1 , wherein the bump comprises a protrusion extending outward from horizontally extending surfaces to a position that is laterally surrounded by the molding compound.

10. A package assembly, comprising:

a bump on a first substrate;

a no-flow underfill layer on a conductive region of a second substrate;

a mask layer on the second substrate and laterally surrounding the no-flow underfill layer, wherein the bump is in contact with the conductive region and is laterally separated from the mask layer by the no-flow underfill layer and wherein the no-flow underfill layer physically contacts an entirety of a sidewall of the mask layer; and wherein the no-flow underfill layer has an exterior curved surface continuously extending from a first end contacting the mask layer to a second end contacting the bump.

11. The package assembly of claim 10 , wherein the no-flow underfill layer extends to a first height above the second substrate that is greater than a second height of the mask layer above the second substrate.

12. The package assembly of claim 10 , wherein the no-flow underfill layer is directly over the second substrate at a location between the mask layer and the conductive region.

13. The package assembly of claim 10 ,

wherein the exterior curved surface has a slope that decreases from the mask layer to the bump.

14. The package assembly of claim 13 , wherein the slope of the exterior curved surface monotonically decreases from the mask layer to the bump.

15. The package assembly of claim 10 , further comprising:

a molding compound on the first substrate and laterally surrounding the bump, wherein a top surface of the no-flow underfill layer facing the molding compound is below a bottom surface of the molding compound.

16. A package assembly, comprising:

a bump on a first substrate;

a no-flow underfill layer on a conductive region over a second substrate, wherein the no-flow underfill layer has a curved surface extending from a top of the conductive region to a top of the no-flow underfill layer; and

wherein the bump extends completely through the no-flow underfill layer to contact the conductive region, wherein the no-flow underfill layer has an curved exterior surface facing away from the bump and the second substrate, and wherein the bump comprises a curved metal surface that directly contacts an entirety of the curved surface of the no-flow underfill layer.

17. The package assembly of claim 16 , further comprising:

a mask layer on the second substrate and laterally surrounding the no-flow underfill layer, wherein the no-flow underfill layer is disposed directly over the first substrate laterally between opposing outer sidewalls of the conductive region and sidewalls of the mask layer.

18. The package assembly of claim 17 , wherein the no-flow underfill layer comprises an epoxy resin having a first height above the second substrate that is greater than a second height of the mask layer above the second substrate.

19. The package assembly of claim 17 , wherein a width of the no-flow underfill layer decreases as a height of the no-flow underfill layer over the second substrate increases.

20. The package assembly of claim 17 , wherein the bump extends from above a top surface of the no-flow underfill layer to a lower surface of the no-flow underfill layer contacting the conductive region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2017
From: LIN, HUNG-JEN; WANG, TSUNG-DING; LEE, CHIEN-HSIUN; LU, WEN-HSIUNG; CHENG, MING-DA; LIU, CHUNG-SHI
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 043664/0335 →
Continuity (4)
Continuation 14713476 · May 15, 2015
Division 13427787 · Mar 22, 2012
Provisional Application 61590255 · Jan 24, 2012
Related Publication 20180012860A1 · Jan 11, 2018