Semiconductor devices having gate structures with skirt regions

1. A semiconductor device comprising:

an active fin protruding from a substrate and extending in a first direction;

a gate structure extending in a second direction that intersects the first direction, the gate structure on the active fin; and

a field insulation layer on a bottom portion of a long side of the active fin, an intersection of a top surface of the field insulation layer and the active fin defining at least one line segment,

wherein the gate structure includes a skirt that extends outwardly in the first direction to cover a portion of the at least one line segment while leaving another portion of the at least one line segment exposed,

wherein a first distance between a plane that longitudinally bisects the gate structure and an entirety of an outer edge of a bottom surface of the skirt strictly decreases with increasing distance from the active fin, and

wherein a second distance between the plane that longitudinally bisects the gate structure and an entirety of an outer edge of a sidewall of the skirt strictly decreases with increasing height, above the substrate.

2. The semiconductor device of claim 1 , wherein the gate structure comprises:

a gate insulation layer;

a work function control layer on the gate insulation layer; and

a conductive layer on the work function control layer.

3. The semiconductor device of claim 2 , wherein the work function control layer includes a first metal and the conductive layer includes a second metal that is different than the first metal.

4. The semiconductor device of claim 1 , wherein a portion of a side of the gate structure that is above the active fin defines a vertically extending plane, and wherein the skirt curves outwardly from the vertically extending plane in the first direction to contact the long side of the active fin.

5. The semiconductor device of claim 1 , wherein the gate structure includes a first region that is adjacent the long side of the active fin that includes the skirt and a second region that is spaced apart from the long side of the active fin, that does not include the skirt, the first region of the gate structure having a greater width than the second region of the gate structure.

6. The semiconductor device of claim 1 , further comprising a device isolation layer that extends in the second direction from a first end of the active fin,

wherein a top surface of the device isolation layer is lower than a top surface of the active fin and the gate structure is on the top surface of the device isolation layer and on the top surface of the active fin.

7. The semiconductor device of claim 6 , wherein a first portion of the gate structure extends below the top surface of the active fin and a second portion of the gate structure is above the top surface of the active fin.

8. The semiconductor device of claim 1 , further comprising a dummy gate structure extending in the second direction to cross the active fin, the active fin having an end positioned under the dummy gate structure, wherein the dummy gate structure includes a first skirt where a first side of the dummy gate structure extends outwardly in the first direction to contact a side surface of the active fin, and wherein a second side of the dummy gate structure that is opposite the first side of the dummy gate structure is a planar side surface that does not include any skirt.

9. The semiconductor device of claim 1 , wherein an outer surface of the skirt has a concave profile.

10. A semiconductor device comprising:

an active fin protruding from a substrate and extending in a first direction;

a gate structure extending in a second direction that intersects the first direction, the gate structure crossing the active fin; and

a dummy gate structure extending in the second direction to cross the active fin, the active fin having an end positioned under the dummy gate structure,

wherein the dummy gate structure includes a first skirt where a first side of the dummy gate structure extends outwardly in the first direction to contact a side surface of the active fin,

wherein the gate structure includes a second skirt where a first side of the gate structure extends outwardly in the first direction to contact the side surface of the active tin and a third skirt where a second side of the gate structure that is opposite the first side extends outwardly in the first direction to contact the side surface of the active fin,

wherein a second side of the dummy gate structure that is opposite the first side of the dummy gate structure is a planar side surface that does not include any skirt,

wherein an outer surface of the first skirt has a concave profile in a firs plane defined by the first direction and the second direction and in a second plane that is perpendicular to the first plane, and

wherein an outer surface of the second skirt has a concave profile in the first plane and in the second plane.

11. The semiconductor device of claim 10 , wherein each of the dummy gate structure and the gate structure comprises: a gate insulation layer, a work function control layer on the gate insulation layer and including a first metal; and a conductive layer on the work function control layer and including a second metal that is different than the first metal.

12. The semiconductor device of claim 10 , wherein the gate structure comprises:

a gate insulation layer;

a work function control layer on the gate insulation layer and including a first metal; and

a first conductive layer on the work function control layer and including a second metal,

wherein the dummy gate structure includes a second conductive layer including silicon.

13. The semiconductor device of claim 10 , further comprising a device isolation layer extending in the second direction from a first end of the active fin,

wherein a top surface of the device isolation layer is lower than a top surface of the active fin and the dummy gate structure overlaps the device isolation layer and the active fin.

14. The semiconductor device of claim 10 , wherein a first distance between a plane that longitudinally bisects the gate structure and an entirety of an outer edge of a bottom surface of the second skirt strictly decreases with increasing distance from the active fin and a second distance between the plane that longitudinally bisects the gate structure and an entirety of an outer edge of a sidewall of the second skirt strictly decreases with increasing height above the substrate.

15. A semiconductor device, comprising:

a substrate;

an active fin that protrudes upwardly from the substrate and that extends in a first direction; and

a gate structure that extends in a second direction to cross the active fin,

wherein a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin,

wherein the lower portion of the gate structure includes a skirt that extends outwardly in the first direction, and wherein the lower portion of the gate structure that includes the skirt has the first width, and

wherein a first distance between a plane that longitudinally bisects the gate structure and entirety of an outer edge of a bottom surface of the skirt strictly decreases with increasing distance from the active fin and a second distance between the plane that longitudinally bisects the gate structure and an entirety of an outer edge of a sidewall of the skirt strictly decreases with increasing height above the substrate.

16. The semiconductor device of claim 15 , wherein a third width of an upper portion of the gate structure that is above a top surface of the active fin is less than the first width.

17. The semiconductor device of claim 15 , wherein an upper portion of the gate structure that is above a top surface of the active fin defines a vertical plane, and wherein the skirt extends outwardly in the first direction from the vertical plane.

18. The semiconductor device of claim 15 , further comprising:

a dummy gate structure that extends in the second direction to cross the active fin so that an end of the active fin is positioned under the dummy structure; and

a device isolation layer extending in the second direction along a first side of the dummy gate structure that does not cross the active fin,

wherein a top surface of the device isolation layer is lower than a top surface of the active fin and the first side of the dummy gate structure overlaps the device isolation layer and a second side of the dummy gate structure that is opposite the first side overlaps the active fin, and

wherein the dummy gate structure includes a first skirt where the second side of the dummy gate structure extends outwardly in the first direction to contact a side surface of the active fin, and wherein the first side of the dummy gate structure is a planar side surface that does not include any skirt.

19. The semiconductor device of claim 15 , wherein an outer surface of the skirt has a concave profile.