Semiconductor device, wireless sensor, and electronic device
An object is to reduce power consumption of an analog-digital converter circuit. An analog potential obtained in a sensor or the like is held in a sample-and-hold circuit including a transistor with an extremely low off-state current. In the sample-and-hold circuit, the analog potential is held in a node which is able to hold a charge by turning off the transistor. Then, power supply to a buffer circuit or the like included in the sample-and-hold circuit is stopped to reduce power consumption. In a structure where a potential is held in each node, power consumption can be further reduced when a transistor with an extremely low off-state current is connected to a node holding a potential of a comparator, a successive approximation register, a digital-analog converter circuit, or the like, and power supply to these circuits is stopped.
1. A semiconductor device comprising:
a sample-and-hold circuit including a transistor including an oxide semiconductor containing indium and oxide in a channel formation region and a capacitor;
a comparator electrically connected to one of a source and a drain of the transistor and the capacitor;
a successive approximation register electrically connected to the comparator;
a digital-analog converter circuit electrically connected to the successive approximation register and the comparator; and
a timing controller electrically connected to a gate of the transistor, the successive approximation register, and the digital-analog converter circuit,
wherein the other of the source and the drain of the transistor is electrically connected to an input terminal of the sample-and-hold circuit.
2. The semiconductor device according to claim 1 ,
wherein the timing controller is configured to output a signal for controlling an on/off state of the transistor.
3. An electronic device comprising:
the semiconductor device according to claim 1 ; and
a display portion.
4. A wireless sensor comprising:
the semiconductor device according to claim 1 ;
an antenna;
an integrated circuit portion including a memory circuit; and
a sensor circuit.
5. The wireless sensor according to claim 4 ,
wherein the memory circuit comprises a third transistor and a fourth transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor,
wherein the one of the source and the drain of the third transistor is configured to hold a charge by turning off the third transistor, and
wherein a channel formation region of the third transistor includes an oxide semiconductor.
6. The wireless sensor according to claim 5 ,
wherein a channel formation region of the fourth transistor includes silicon.
7. The semiconductor device according to claim 1 ,
wherein a normalized off-state current per micrometer in channel width of the transistor is 1×10 −18 A or less at room temperature.
8. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor include a crystal.
9. The semiconductor device according to claim 1 ,
wherein the sample-and-hold circuit further includes a first inverter, a second inverter, and an MOS capacitor.
10. A semiconductor device comprising:
a sample-and-hold circuit including a transistor including an oxide semiconductor containing indium and oxide in a channel formation region and a capacitor;
a comparator;
a successive approximation register;
a digital-analog converter circuit; and
a timing controller,
wherein one of a source and a drain of the transistor is electrically connected to an input terminal of the sample-and-hold circuit
wherein the other of the source and the drain of the transistor is configured to hold a charge by turning off the transistor, and
wherein the semiconductor device is configured to stop supply of a power supply voltage to the sample-and-hold circuit after holding the charge.
11. The semiconductor device according to claim 10 ,
wherein the timing controller is configured to output a signal for controlling an on/off state of the transistor.
12. An electronic device comprising:
the semiconductor device according to claim 10 ; and
a display portion.
13. A wireless sensor comprising:
the semiconductor device according to claim 10 ;
an antenna;
an integrated circuit portion including a memory circuit; and
a sensor circuit.
14. The wireless sensor according to claim 13 ,
wherein the memory circuit comprises a third transistor and a fourth transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor,
wherein the one of the source and the drain of the third transistor is configured to hold a second charge by turning off the third transistor, and
wherein a channel formation region of the third transistor includes an oxide semiconductor.
15. The wireless sensor according to claim 14 ,
wherein a channel formation region of the fourth transistor includes silicon.
16. The semiconductor device according to claim 10 ,
wherein a normalized off-state current per micrometer in channel width of the transistor is 1×10 −18 A or less at room temperature.
17. The semiconductor device according to claim 10 ,
wherein the oxide semiconductor include a crystal.
18. The semiconductor device according to claim 10 ,
wherein the sample-and-hold circuit further includes a first inverter, a second inverter, and an MOS capacitor.