IP Library Granted Patent US 10,199,476
Granted Patent B2
US 10,199,476 · App. 15/841,676 · Granted Feb 5, 2019

Semiconductor device and manufacturing method of semiconductor device

Inventors: Tatsuo Nakayama (Ibaraki, JP); Hironobu Miyamoto (Ibaraki, JP); Yasuhiro Okamoto (Ibaraki, JP)
Assignee: Renesas Electronics Corporation
H01L29/66431H01L29/1066H01L29/205H01L29/42376H01L29/66462H01L29/7783H01L29/7786H01L29/7787H01L29/7789H01L29/2003H01L29/207H01L29/402
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Quick Facts
Patent No.
US 10,199,476
App. No.
15/841,676
Granted
Feb 5, 2019
Kind
B2
Abstract

A mesa portion of a semiconductor device, which includes a channel base layer formed of a first nitride semiconductor layer, a channel layer formed of a second nitride semiconductor layer, a barrier layer formed of a third nitride semiconductor layer, a mesa-type fourth nitride semiconductor layer, a gate insulating film that covers the mesa portion, and a gate electrode formed over the gate insulating film, is used as a co-doped layer. The mesa portion is used as the co-doped layer, so that interface charges generated at an interface between the gate insulating film and the mesa portion can be cancelled by p-type impurity or n-type impurity in the co-doped layer and a threshold potential can be improved. Further, the fourth nitride semiconductor layer is n-type until the gate insulating film is formed, and the fourth nitride semiconductor layer is made neutral or p-type after the gate insulating film is formed.

Claims (31)

1. A semiconductor device comprising:

a first nitride semiconductor layer;

a second nitride semiconductor layer that is formed over the first nitride semiconductor layer;

a third nitride semiconductor layer that is formed over the second nitride semiconductor layer;

a mesa-type fourth nitride semiconductor layer that is formed over the third nitride semiconductor layer;

a source electrode that is formed over the third nitride semiconductor layer and on one side of the fourth nitride semiconductor layer;

a drain electrode that is formed over the third nitride semiconductor layer and on the other side of the fourth nitride semiconductor layer;

a gate insulating film that covers the fourth nitride semiconductor layer; and

a gate electrode that is formed over the gate insulating film,

wherein an electron affinity of the second nitride semiconductor layer is greater than an electron affinity of the first nitride semiconductor layer and is greater than an electron affinity of the third nitride semiconductor layer,

wherein an electron affinity of the fourth nitride semiconductor layer is greater than or equal to the electron affinity of the first nitride semiconductor layer, and

wherein the fourth nitride semiconductor layer has p-type impurity and n-type impurity and concentration of the p-type impurity is greater than concentration of the n-type impurity.

2. The semiconductor device according to claim 1 ,

wherein the concentration of the p-type impurity in the fourth nitride semiconductor layer is five times or more the concentration of the n-type impurity.

3. The semiconductor device according to claim 1 ,

wherein the concentration of the p-type impurity in the fourth nitride semiconductor layer is ten times or more the concentration of the n-type impurity.

4. The semiconductor device according to claim 1 ,

wherein a product of the concentration of the p-type impurity in the fourth nitride semiconductor layer and a film thickness of the fourth nitride semiconductor layer is greater than or equal to 1×10 12 cm −2 .

5. The semiconductor device according to claim 1 ,

wherein the fourth nitride semiconductor layer contains hydrogen; and

wherein the concentration of the p-type impurity is greater than a sum of the concentration of the n-type impurity and concentration of the hydrogen.

6. The semiconductor device according to claim 1 , further comprising:

a fifth nitride semiconductor layer that is formed over the third nitride semiconductor layer,

wherein the fourth nitride semiconductor layer is formed over the fifth nitride semiconductor layer.

7. The semiconductor device according to claim 6 ,

wherein the fifth nitride semiconductor layer is mesa type, and

wherein a laminated body of the fifth nitride semiconductor layer and the fourth nitride semiconductor layer is formed over the third nitride semiconductor layer.

8. The semiconductor device according to claim 1 ,

wherein planar shapes of the fourth nitride semiconductor layer, the gate insulating film, and the gate electrode are substantially the same.

9. The semiconductor device according to claim 1 ,

wherein aside surface of the mesa-type fourth nitride semiconductor layer has a tapered shape.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2017
From: NAKAYAMA, TATSUO; MIYAMOTO, HIRONOBU; OKAMOTO, YASUHIRO
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044398/0938 →
Priority Claims (1)
JP 2017-012688 · Jan 27, 2017 · national
Continuity (1)
Related Publication 20180219089A1 · Aug 2, 2018