Apparatus and method for correcting at least one bit error within a coded bit sequence

1. A decoding apparatus to decode at least one bit error within a coded bit sequence, the apparatus comprising:

an error syndrome generator, with one or more microcontrollers, configured to:

generate a multiplication of a check matrix (H) with a coded bit sequence to derive an error syndrome, wherein the check matrix (H) comprises a first sub-matrix (H u ), a second sub-matric (H a ) and a third sub-matrix (H c );

determine lines of the third sub-matrix (H c ) that are linearly independent from each other, and determine lines of the second sub-matrix (H a ) that are linearly independent from each other and are all different from lines of the first sub-matrix (H u ) and the lines of the third sub-matrix (H c ) by at least one bit;

generate a multiplication of the first sub-matrix (H u ) with a first group of bits of the coded bit sequence, a multiplication of the second sub-matrix (H a ) with a second group of bits of the coded bit sequence, and a multiplication of the third sub-matrix (H c ) with a third group of bits of the coded bit sequence to determine the error syndrome of the coded bit sequence; and

a bit error corrector, with the one or more microcontrollers, configured to detect every 1-bit address error and every 2-bit address error and correct the at least one bit error using the error syndrome;

wherein the first group of bits comprises information bits, the second group of bits comprises address bits and the third group of bits comprises check bits;

wherein the check matrix (H) comprises a check matrix of a shortened Hamming code, a shortened Hsiao-code, a shortened bit error correcting BCH-code or a shortened bit error correcting BCH-code with an included parity.

2. Method for decoding at least one bit error within a coded bit sequence, the method comprising:

multiplying, via an error syndrome generator with one or more microcontrollers, a check matrix (H) with a coded bit sequence to derive an error syndrome, wherein the check matrix (H) comprises a first sub-matrix (H u ), a second sub-matrix (H a ) and a third sub-matrix (H c ), comprising:

determining lines of the third sub-matrix (H c ) that are linearly independent from each other, and determining lines of the second sub-matrix (H a ) that are linearly independent from each other and that are all different by at least one bit from lines of the first sub-matrix (H u ) and the lines of the third sub-matrix (H c );

multiplying, via the error syndrome generator with the one or more microcontrollers, the first sub-matrix (H u ) with a first group of bits of the coded bit sequence;

multiplying, via the error syndrome generator with the one or more microcontrollers, a second sub-matrix (H a ) with a second group of bits of the coded bit sequence; and

multiplying, via the error syndrome generator with the one or more microcontrollers, the third sub-matrix (H c ) with a third group of bits of the coded bit sequence;

detecting every 1-bit address error and every 2-bit address error; and

correcting, via a bit error corrector with the one or more microcontrollers, the at least one bit error using the error syndrome;

wherein the first group of bits comprises information bits, the second group of bits comprises address bits and the third group of bits comprises check bits, and

wherein the check matrix (H) comprises a check matrix of a shortened Hamming code, a shortened Hsiao-code, a shortened bit error correcting BCH-code or a shortened bit error correcting BCH-code with an included parity.

3. A non-transitory computer readable storage medium for performing a method of a computer program for decoding at least one bit error within a coded bit sequence in response to the computer program executing the method on one or more microcontrollers, the method comprising:

multiplying, via one or more microcontrollers, a check matrix (H) with a coded bit sequence to derive an error syndrome, wherein the check matrix (H) comprises a first sub-matrix (H u ), a second sub-matrix (H a ) and a third sub-matrix (H c ) comprising:

determining lines of the third sub-matrix (H c ) that are linearly independent from each other, and determining lines of the second sub-matrix (H a ) that are linearly independent from each other and that are all different from lines of the first sub-matrix (H u ) and the lines of the third sub-matrix (H c ) by at least one bit;

multiplying, via the one or more microcontrollers, the first sub-matrix (H u ) with a first group of bits of the coded bit sequence;

multiplying, via the one or more microcontrollers, a second sub-matrix (H a ) with a second group of bits of the coded bit sequence; and

multiplying, via the one or more microcontrollers, the third sub-matrix (H c ) with a third group of bits of the coded bit sequence;

determining an error syndrome using a hardware error syndrome generator of a coded bit sequence derived by a multiplication of a check matrix (H) with the coded bit sequence;

detecting every 1-bit address error and every 2-bit address error; and

correcting, via a bit error corrector with the one or more microcontrollers, the at least one bit error using the error syndrome;

wherein the first group of bits comprises information bits, the second group of bits comprises address bits and the third group of bits comprises check bits, and

wherein the check matrix (H) comprises a check matrix of a shortened Hamming code, a shortened Hsiao-code, a shortened bit error correcting BCH-code or a shortened bit error correcting BCH-code with included parity.

4. The decoding apparatus according to claim 1 , further comprising:

a storage adapted to store the coded bit sequence; and

an address generator adapted to generate an address (a) defining where the coded bit sequence is stored in the storage.

5. The decoding apparatus according to claim 4 , further comprising:

an AND gate, wherein the AND gate is coupled to the storage; and

a NOR gate, wherein the NOR gate is coupled to the storage.

6. The decoding apparatus according to claim 1 , wherein the error syndrome generator is further configured to store at least the first group of bits and the third group of bits of the coded bit sequence at an address of an addressable storage indicated by the second group of bits.

7. The method according to claim 2 , further comprising: storing at least the first group of bits and the third group of bits of the coded bit sequence at an address of an addressable storage indicated by the second group of bits.

8. The computer readable storage medium according to claim 3 , wherein the method further comprises: storing at least the first group of bits and the third group of bits of the coded bit sequence at an address of an addressable storage indicated by the second group of bits.

9. The decoding apparatus according to claim 1 , wherein the bit error corrector is further configured to detect an error All-0 and an error All-1 in different address values of a storage.

10. The method according to claim 2 , further comprising: detecting an error All-0 and an error All-1 in different address values of a storage.

11. The computer readable storage medium according to claim 3 , the method further comprising:

detecting an error All-0 and an error All-1 in different address values of a storage.