Method and apparatus for saving power, including at least two power saving modes

1. A device, comprising:

a first core circuit including processing circuits, the processing circuits configured to:

measure an active current and a leakage current of the first core circuit under a present operation condition;

have at least a first power saving mode and a second power saving mode, wherein the second power saving mode is a deeper power saving or deeper sleep mode than the first power saving mode, the first power saving mode having (i) a first latency, which is a first amount of time the processing circuits take to enter to the first power saving mode or exit from the first power saving mode, the second power saving mode having (ii) a second latency, which is a second amount of time the processing circuits take to enter to the second power saving mode or exit from the second power saving mode, the first latency being smaller than the second latency;

determine a target residency time as a function of the active current, the leakage current, the first latency, and the second latency;

determine a power saving mode for the processing circuits based on the determined target residency time, wherein (a) the determined power saving mode is the first power saving mode when a predicted residency time of the processing circuits is shorter than the determined target residency time and (b) the determined power saving mode is the second power saving mode when the predicted residency time of the processing circuits is longer than the determined target residency time; and

a power mode control circuit configured to receive information that is indicative of the power saving mode from the processing circuits, and control the processing circuits to enter the determined power saving mode.

2. The device of claim 1 , wherein the processing circuits are configured to compare the predicted residency time with the determined target residency time.

3. The device of claim 1 , wherein the power mode control circuit further comprises:

a power switch circuit configured to provide an adjustable supply voltage to the processing circuits; and

a clock gating circuit configured to provide a gated clock to the processing circuits.

4. The device of claim 3 , wherein the clock gating circuit is configured to disable transitions in the gated clock and the power switch circuit is configured to maintain the supply voltage to the processing circuits to configure the processing circuits in the first power saving mode, and the power switch circuit is configured to switch off the supply voltage to the processing circuits to configure the processing circuits in the second power saving mode.

5. The device of claim 1 , wherein the processing circuits are first processing circuits in the first core circuit, and the power mode control circuit is a first power mode control circuit in the first core circuit, and the device further comprises:

a second core circuit comprising:

second processing circuits configured to have at least the first power saving mode and the second power saving mode, the second processing circuits configured to determine a power saving mode for the second processing circuits; and

a second power mode control circuit configured to receive information from the second processing circuits that is indicative of the determined power saving mode for the second processing circuits, and control the second processing circuits to enter the determined power saving mode.

6. A method for power saving, comprising:

measuring an active current and a leakage current of a core circuit under a present operation condition by processing circuits;

implementing at least a first power saving mode and a second power saving mode, wherein the second power saving mode is a deeper power saving or deeper sleep mode than the first power saving mode, the first power saving mode having (i) a first latency, which is a first amount of time the processing circuits take to enter to the first power saving mode or exit from the first power saving mode, the second power saving mode having (ii) a second latency, which is a second amount of time the processing circuits take to enter to the second power saving mode or exit from the second power saving mode, the first latency being smaller than the second latency;

determining a target residency time as a function of the active current, the leakage current, the first latency, and the second latency;

determining a power saving mode for the processing circuits based on the determined target residency time, wherein (a) the determined power saving mode is the first power saving mode when a predicted residency time of the processing circuits is shorter than the determined target residency time and (b) the determined power saving mode is the second power saving mode when the predicted residency time of the processing circuits is longer than the determined target residency time; and

controlling to enter the determined power saving mode.

7. The method of claim 6 , further comprising:

predicting a residency time for power saving; and

comparing the predicted residency time with the determined target residency time.

8. The method of claim 6 , wherein controlling the processing circuits to enter the determined power saving mode further comprises:

providing a controllable supply voltage to the processing circuits; and

providing a gated clock to the processing circuits.

9. The method of claim 8 , further comprising:

disabling transitions in the gated clock; and

maintaining the supply voltage to the processing circuits to configure the processing circuits in the first power saving mode.

10. The method of claim 9 , further comprising:

switching off the supply voltage to the processing circuits to configure the processing circuits in the second power saving mode.

11. An apparatus, comprising:

a memory configured to store software instructions to determine a power saving mode; and

processing circuits configured to measure an active current and a leakage current of a core circuit under a present operation condition and have at least a first power saving mode and a second power saving mode, wherein the second power saving mode is a deeper power saving or deeper sleep mode than the first power saving mode, the first power saving mode having (i) a first latency, which is a first amount of time the processing circuits take to enter to the first power saving mode or exit from the first power saving mode, the second power saving mode having (ii) a second latency, which is a second amount of time the processing circuits take to enter to the second power saving mode or exit from the second power saving mode, the first latency being smaller than the second latency, the processing circuits further configured to execute the software instructions to:

determine a target residency time as a function of the active current, the leakage current, the first latency, and the second latency;

select a power saving mode from the at least the first power saving mode and the second power saving mode for the processing circuits based on the determined target residency time, wherein (a) the determined power saving mode is the first power saving mode when a predicted residency time of the processing circuits is shorter than the determined target residency time and (b) the determined power saving mode is the second power saving mode when the predicted residency time of the processing circuits is longer than the determined target residency time; and

enter the determined power saving mode.

12. The apparatus of claim 11 , wherein the processing circuits are configured to execute the software instructions to compare the predicted residency time with the determined target residency time.

13. The apparatus of claim 11 , wherein the processing circuits include:

a power switch circuit configured to provide an adjustable supply voltage to the processing circuits; and

a clock gating circuit configured to provide a gated clock to the processing circuits.

14. The apparatus of claim 13 , wherein

the clock gating circuit is further configured to disable transitions in the gated clock; and

the power switch circuit is further configured to:

maintain the adjustable supply voltage to configure the processing circuits in the first power saving mode, and

switch off the adjustable supply voltage to configure the processing circuits in the second power saving mode.