Semiconductor device and manufacturing method of the same

1. A semiconductor device, comprising:

a semiconductor substrate;

a front surface electrode being in contact with a front surface of the semiconductor substrate;

a rear surface electrode being in contact with a rear surface of the semiconductor substrate,

wherein

the semiconductor substrate comprises:

an element region overlapping with a contact surface between the front surface electrode and the semiconductor substrate in a planar view along a thickness direction of the semiconductor substrate, and comprising a semiconductor element configured to electrically connect the front surface electrode and the rear surface electrode; and

a peripheral voltage withstanding region located around the element region and comprising:

a plurality of p-type guard rings exposed on the front surface and surrounding the element region in a pattern of layers of rings; and

an n-type peripheral drift region separating the plurality of guard rings from each other,

wherein the plurality of guard rings comprises:

a plurality of inner circumferential guard rings; and

a plurality of outer circumferential guard rings located on an outer circumferential side with respect to the inner circumferential guard rings and having a width narrower than a width of the inner circumferential guard rings,

an interval between the inner circumferential guard rings is narrower than an interval between the outer circumferential guard rings,

wherein each of the inner circumferential guard rings comprises:

a first high concentration region having a p-type impurity concentration that is higher than ten percent of a peak value of a p-type impurity concentration of the inner circumferential guard ring; and

a first low concentration region having a p-type impurity concentration that is equal to or less than ten percent of the peak value of the p-type impurity concentration of the inner circumferential guard ring and located between the corresponding first high concentration region and the peripheral drift region,

each of the outer circumferential guard rings comprises:

a second high concentration region having a p-type impurity concentration that is higher than ten percent of a peak value of a p-type impurity concentration of the outer circumferential guard ring; and

a second low concentration region having a p-type impurity concentration that is equal to or lower than ten percent of the peak value of the p-type impurity concentration of the outer circumferential guard ring and located between the corresponding second high concentration region and the peripheral drift region, and

a width of a portion of each first low concentration region is wider than a width of a portion of each second low concentration region, the portion of each first low concentration region being exposed on the front surface and being adjacent to the corresponding first high concentration region on the outer circumferential side, and the portion of each second low concentration region being exposed on the front surface and being adjacent to the corresponding second high concentration region on the outer circumferential side.

2. The semiconductor device of claim 1 , wherein

the element region further comprises:

a plurality of contact p-type regions being in contact with the front surface electrode and extending in stripe shapes with intervals therebetween;

an n-type main drift region being in Schottky contact h front surface electrode at positions between the plurality of contact p-type regions; and

an n-type cathode region being in ohmic contact with the rear surface electrode and being in contact with the main drift region,

each of the contact p-type regions comprises:

a third high concentration region having a p-type impurity concentration that is higher than ten percent of a peak value of a p-type impurity concentration of the contact p-type region; and

a third low concentration region having a p-type impurity concentration that is equal to or lower than ten percent of the peak value of the p-type impurity concentration of the contact p-type region and located between the corresponding third high concentration region and the main drift region, and

a width of a portion of each third low concentration region is narrower than the width of the portion of each second low concentration region, the portion of each third low concentration region being exposed on the front surface.

3. A method of manufacturing the semiconductor device of claim 1 , the method comprising:

forming a mask on a front surface of a semiconductor wafer, the mask comprising inner circumferential openings and outer circumferential openings;

forming the inner circumferential guard rings by implanting p-type impurities to the front surface of the semiconductor water within the inner circumferential openings and forming the outer circumferential guard rings by implanting p-type impurities to the front surface of the semiconductor wafer within the outer circumferential openings,

wherein

an inclination angle of a lateral surface of each inner circumferential opening is larger than an inclination angle of a lateral surface of each outer circumferential opening.