IP Library Granted Patent US 10,209,587
Granted Patent B2
US 10,209,587 · App. 15/702,819 · Granted Feb 19, 2019

Array substrate, liquid crystal display panel and display device

Inventor: Hao Wu (Xiamen, CN)
Assignee: XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD.
G02F1/136227G02F1/137G02F1/1368G02F1/13338G02F1/133345G02F1/136286G06F3/044G06F3/0412G02F1/134336G02F2001/13606G02F2001/13685G02F2001/13712G02F2201/121G02F2201/122G02F2201/123
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Quick Facts
Patent No.
US 10,209,587
App. No.
15/702,819
Granted
Feb 19, 2019
Kind
B2
Abstract

The present disclosure provides an array substrate, including: a base substrate, a plurality of scan lines; a plurality of data lines arranged by intersecting with the plurality of scan lines; a plurality of thin film transistors arranged in a matrix, each thin film transistor includes a gate electrode, an active layer and a drain electrode; a planarization layer covering the gate electrode, the active layer and the drain electrode, a position of the planarization layer corresponding to the drain electrode is provided with a through hole penetrating through the planarization layer, and the drain electrode is located in the through hole; a filling electrode, located in the through hole and connected with the drain electrode and covers the drain electrode; and a pixel electrode, indirectly connected with the drain electrode through the filling electrode.

Claims (52)

1. An array substrate, comprising:

a base substrate;

a plurality of scan lines;

a plurality of data lines intersecting with the plurality of scan lines;

a plurality of thin film transistors arranged in a matrix, each thin film transistor comprising a gate electrode, an active layer and a drain electrode;

a planarization layer covering the gate electrode, the active layer and the drain electrode,

a filling electrode; and

a pixel electrode;

wherein a through hole is defined in a part of the planarization layer corresponding to the drain electrode, a width of the drain electrode is smaller than a width of a bottom of the through hole, and the drain electrode is located in an interior of the through hole;

wherein the filling electrode is located in the through hole, and the filling electrode is connected with the drain electrode and covers the drain electrode; and

wherein the pixel electrode extends through the through hole to connect with the filling electrode.

2. The array substrate according to claim 1 , further comprising:

a common electrode, located between the planarization layer and the pixel electrode; and

a second insulating layer, located between the common electrode and the pixel electrode;

wherein the filling electrode and the common electrode are formed in a same layer.

3. The array substrate according to claim 2 , further comprising:

a first insulating layer, provided between the planarization layer and the common electrode; and

an auxiliary filling piece, filled between each of two ends of the drain electrode and a side wall of the through hole;

wherein the auxiliary filling piece and the first insulating layer are formed in a same layer.

4. The array substrate according to claim 1 , further comprising:

a touch electrode; and

a plurality of touch signal lines connected with a corresponding touch electrode;

wherein the filling electrode comprises a first electrode, and the first electrode and the touch signal lines are formed in a same layer.

5. The array substrate according to claim 4 , wherein the touch electrode is located between the planarization layer and the pixel electrode, and a second insulating layer is provided between the common electrode and the pixel electrode.

6. The array substrate according to claim 5 , wherein the filling electrode further comprises a second electrode, and the second electrode and the touch electrode are formed in a same layer.

7. The array substrate according to claim 4 , wherein the touch signal lines is located between the planarization layer and the touch electrode, and a first insulating layer is provided between the touch signal lines and the touch electrode.

8. The array substrate according to claim 6 , wherein during a display period, the touch electrode also serves as a common electrode.

9. A liquid crystal display panel, comprising an array substrate, a color film substrate arranged opposite to the array substrate, and a liquid crystal layer arranged between the array substrate and the color film substrate;

wherein the array substrate comprises:

a base substrate;

a plurality of scan lines;

a plurality of data lines intersecting with the plurality of scan lines;

a plurality of thin film transistors arranged in a matrix, each thin film transistor comprising a gate electrode, an active layer and a drain electrode;

a planarization layer covering the gate electrode, the active layer and the drain electrode,

a filling electrode; and

a pixel electrode;

wherein a through hole is defined in a part of the planarization layer corresponding to the drain electrode, a width of the drain electrode is smaller than a width of a bottom of the through hole, and the drain electrode is located in an interior of the through hole;

wherein the filling electrode is located in the through hole, and the filling electrode is connected with the drain electrode and covers the drain electrode; and

wherein the pixel electrode extends through the through hole to connect with the filling electrode.

10. The liquid crystal display panel according to claim 9 , wherein the liquid crystal layer comprises a negative liquid crystal.

11. A display device, comprising a liquid crystal display panel, wherein the liquid crystal display panel comprises an array substrate, a color film substrate arranged opposite to the array substrate, and a liquid crystal layer arranged between the array substrate and the color film substrate;

wherein the array substrate comprises:

a base substrate;

a plurality of scan lines;

a plurality of data lines intersecting with the plurality of scan lines;

a plurality of thin film transistors arranged in a matrix, each thin film transistor comprising a gate electrode, an active layer and a drain electrode;

a planarization layer covering the gate electrode, the active layer and the drain electrode,

a filling electrode; and

a pixel electrode;

wherein a through hole is defined in a part of the planarization layer corresponding to the drain electrode, a width of the drain electrode is smaller than a width of a bottom of the through hole, and the drain electrode is located in an interior of the through hole;

wherein the filling electrode is located in the through hole, and the filling electrode is connected with the drain electrode and covers the drain electrode; and

wherein the pixel electrode extends through the through hole to connect with the filling electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2017
From: WU, HAO
To: XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD.
Reel/Frame 043845/0373 →
Priority Claims (1)
CN 2017 1 0418357 · Jun 6, 2017 · national
Continuity (1)
Related Publication 20180348584A1 · Dec 6, 2018
Cited By (1)
US 12,696,489