Memory device and semiconductor device including the same
View Patent ↗A memory device with reduced latency is provided. The memory device includes a burst read mode with a burst length of M 0 (M 0 is an integer greater than or equal to 2), a global sense amplifier array, M 0 local memory cell arrays < 1 > to <M 0 >, and M 0 local sense amplifier arrays < 1 > to <M 0 >. A memory cell includes a transistor and a capacitor. A local memory cell array <J> (J is an integer from 1 to M 0 ) is stacked over a local sense amplifier array <J>. The local memory cell array <J> comprises M 0 blocks <J_ 1 > to <J_M 0 > differentiated by row, The local sense amplifier array <J> in an idle state retains the data of the block <J_J>. The block <J_J> is specified when the local memory cell array <J> is the first local memory cell array to be accessed in a burst read mode.
1. A memory device configured with a burst read mode, comprising:
a global sense amplifier array;
first to M 0 th local memory cell arrays; and
first to M 0 th local sense amplifier arrays,
wherein M 0 is an integer greater than or equal to 2,
wherein a Jth local memory cell array is stacked over a Jth local sense amplifier array,
wherein the Jth local memory cell array comprises first to M 0 th blocks differentiated by row,
wherein the first to M 0 th blocks each comprise a plurality of memory cells,
wherein the memory cells each comprise a capacitor and a transistor,
wherein the Jth local sense amplifier array in an idle state retains data of a Jth block,
wherein the Jth block is specified when the Jth local memory cell array is the first local memory cell array that is accessed in the burst read mode, and
wherein J is an integer from 1 to M 0 .
2. The memory device according to claim 1 ,
wherein one block in each of the first to M 0 th local memory cell arrays is accessed during the burst read mode.
3. The memory device according to claim 1 ,
wherein first to M 0 th blocks are accessed during the burst read mode when a J x th local array comprising the Jth local memory cell array and the Jth local sense amplifier array is specified by an external address signal ADDR, and
wherein 4 is an integer from 1 to M 0 .
4. The memory device according to claim 1 ,
wherein the transistor comprises a metal oxide in a channel formation region.
5. A semiconductor device comprising:
a processor core;
a memory portion; and
a bus,
wherein the memory portion comprises the memory device according to claim 1 , and
wherein the transfer of a signal and data between the processor core and the memory portion is performed through the bus.
6. The semiconductor device according to claim 5 ,
wherein the memory portion comprises at least one of an SRAM, a flash memory, a ferroelectric RAM, a magnetoresistive RAM, a resistive RAM, and a phase-change RAM.
7. An electronic component comprising:
a chip; and
a lead,
wherein the lead is electrically connected to the chip, and
wherein the memory device in claim 1 or the semiconductor device in claim 5 is provided on the chip.
8. An electronic device comprising:
the electronic component according to claim 7 ; and
at least one of a display portion, a touch sensor, a microphone, a speaker, an operation key, and a housing.
9. A memory device configured with a burst read mode with a burst length of M 0 ×M 1 wherein M 0 is an integer greater than or equal to 2, and M 1 is an integer greater than or equal to 1, comprising:
a global sense amplifier array;
first to (M 0 ×M 1 )th local memory cell arrays; and
first to (M 0 ×M 1 )th local sense amplifier arrays,
wherein a Jth local memory cell array is stacked over a Jth local sense amplifier array,
wherein the Jth local memory cell array comprises first to M 0 th blocks differentiated by row,
wherein the first to M 0 th blocks each comprise a plurality of memory cells,
wherein the memory cells each comprise a capacitor and a transistor,
wherein the Jth local sense amplifier array in an idle state retains data of a X 1 th block,
wherein the X 1 th block is specified when the Jth local memory cell array is the first local memory cell array to be accessed in the burst read mode, and
wherein J is an integer from 1 to M 0 ×M 1 and X 1 is an integer from 1 to M 0 .
10. The memory device according to claim 9 ,
wherein one block in each of the first to (M 0 ×M 1 )th local memory cell arrays is accessed during the burst read mode.
11. The memory device according to claim 9 ,
wherein the transistor comprises a metal oxide in a channel formation region.
12. A semiconductor device comprising:
a processor core;
a memory portion; and
a bus,
wherein the memory portion comprises the memory device according to claim 9 , and
wherein the transfer of a signal and data between the processor core and the memory portion is performed through the bus.
13. The semiconductor device according to claim 12 ,
wherein the memory portion comprises at least one of an SRAM, a flash memory, a ferroelectric RAM, a magnetoresistive RAM, a resistive RAM, and a phase-change RAM.
14. An electronic component comprising:
a chip; and
a lead,
wherein the lead is electrically connected to the chip, and
wherein the memory device in claim 9 or the semiconductor device in claim 12 is provided on the chip.
15. An electronic device comprising:
the electronic component according to claim 14 ; and
at least one of a display portion, a touch sensor, a microphone, a speaker, an operation key, and a housing.