Semiconductor package

1. A semiconductor package comprising:

a substrate;

through-electrodes penetrating the substrate;

an insulating pattern provided on the substrate;

first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate, the first bumps being electrically connected to the through-electrodes, respectively; and

at least one second bump disposed between the first bumps, the at least one second bump being electrically insulated from the through-electrodes,

wherein the first bumps and the at least one second bump constitute one row in the first direction,

wherein a level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same level as levels of bottom surfaces of the first bumps from the top surface of the substrate,

wherein the insulating pattern covers a space between the first bumps and covers a space between the first bumps and the at least one second bump,

wherein the insulating pattern has first through-holes overlapping with the through-electrodes, respectively,

wherein the first bumps are provided in the first through-holes, respectively,

wherein the insulating pattern has a second through-hole exposing the top surface of the substrate, and

wherein a second bump is provided in the second through-hole.

2. The semiconductor package as claimed in claim 1 , further comprising:

first pads, each of which is disposed between each of the first bumps and each of the through-electrodes; and

at least one second pad disposed between the at least one second bump and the substrate,

wherein the first pads are electrically connected to the first bumps and the through-electrodes, respectively, and

wherein the at least one second pad is electrically insulated from the through-electrodes.

3. The semiconductor package as claimed in claim 1 , wherein the first bumps and the at least one second bump have thicknesses in a second direction perpendicular to the top surface of the substrate, and

wherein the thicknesses of the first bumps are substantially equal to the thickness of the at least one second bump.

4. The semiconductor package as claimed in claim 1 , wherein the first bumps comprise:

a pair of first bumps spaced apart from each other in the first direction by a first distance, the pair of first bumps being immediately adjacent to each other; and

another pair of first bumps spaced apart from each other in the first direction by a second distance greater than the first distance,

wherein the at least one second bump is provided between the another pair of first bumps.

5. The semiconductor package as claimed in claim 4 , wherein the at least one second bump includes a plurality of second bumps,

wherein ones of the second bumps immediately adjacent to each other are spaced apart from each other in the first direction by a third distance, and

wherein the third distance is substantially equal to or smaller than the first distance.

6. The semiconductor package as claimed in claim 5 , wherein one of the first bumps and one of the second bumps immediately adjacent to each other are spaced apart from each other in the first direction by a fourth distance, and

wherein the fourth distance is substantially equal to or smaller than the first distance.

7. The semiconductor package as claimed in claim 1 , further comprising:

an underfill provided on the substrate to cover the first and second bumps,

wherein an upper portion of each of the first and at least one second bumps includes a solder, and

wherein the underfill is melted at a temperature equal to or lower than a melting point of the solder to have fluidity.

8. The semiconductor package as claimed in claim 7 , wherein the underfill includes a non-conductive film (NCF) or non-conductive paste (NCP).

9. A semiconductor device, comprising:

a first substrate having an active device at a first surface thereof;

a second substrate, the second substrate being bonded to a second surface of the first substrate, opposite the first surface, by a plurality of bumps, the bumps including a plurality of first bumps that have respective electrical connections to through-electrodes penetrating the first substrate to electrically connect to the active device and including a plurality of second bumps interspersed between the first bumps, the second bumps being mounted on an insulating region of the second surface, the first and second bumps being spaced at a regular pitch; and

an underfill layer interposed between the first and second substrates, and contacting the first and second bumps, wherein:

the first bumps are spaced apart from each other in a first direction parallel to the second surface of the first substrate,

at least one second bump of the plurality of second bumps is disposed between the first bumps, the at least one second bump being electrically insulated from the through-electrodes,

the first bumps and the at least one second bump constitute one row in the first direction,

a level of a bottom surface of the at least one second bump from the second surface of the first substrate is a substantially same level as levels of bottom surfaces of the first bumps from the second surface of the first substrate,

an insulating pattern is provided on the first substrate,

the insulating pattern covers a space between the first bumps and covers a space between the first bumps and the at least one second bump,

the insulating pattern has through-holes overlapping with the through-electrodes, respectively,

the first bumps are provided in the through-holes, respectively,

the insulating pattern has a second through-hole exposing the second surface of the first substrate, and

the at least one second bump is provided in the second through-hole.

10. The semiconductor device as claimed in claim 9 , wherein the first and second bumps have centers aligned on a straight line.

11. The semiconductor device as claimed in claim 9 , wherein the underfill layer is from an underfill film pressed between the first and second substrates.

12. The semiconductor device as claimed in claim 9 , wherein the second bumps are electrically floated.

13. The semiconductor device as claimed in claim 9 , wherein the second bumps are electrically isolated from the first bumps.