Scalable SGT structure with improved FOM

1. A shielded gate trench field effect transistor, comprising:

a) a substrate of a first conductivity type;

b) an epitaxial layer of the first conductivity type provided on top of the substrate;

c) a body region of a second conductivity type that is opposite to the first conductivity type formed above the epitaxial layer;

d) a trench formed in the body region and epitaxial layer, wherein the trench is lined with a first dielectric layer and wherein the trench has a pitch less than 1 μm;

e) a shield electrode formed in a lower portion of the trench, wherein the shield electrode is insulated from the epitaxial layer by the first dielectric layer;

f) a gate electrode formed in an upper portion of the trench above the shield electrode, wherein the gate electrode is insulated from the epitaxial layer by the first dielectric layer and insulated from the shield electrode by a second dielectric layer, wherein the first and second dielectric layers have the same thickness; and

g) one or more source regions of the first conductivity type formed in a top surface of the body region, wherein each source region is adjacent a sidewall of the trench.

2. The field effect transistor of claim 1 , wherein the trench has a pitch about 0.6 um.

3. A shielded gate trench field effect transistor, comprising:

a) a substrate of a first conductivity type;

b) an epitaxial layer of the first conductivity type provided on top of the substrate;

c) a body region of a second conductivity type that is opposite to the first conductivity type formed above the epitaxial layer;

d) a trench formed in the body region and epitaxial layer, wherein the trench is lined with a first dielectric layer;

e) a shield electrode formed in a lower portion of the trench, wherein the shield electrode is insulated from the epitaxial layer by the first dielectric layer;

f) a gate electrode formed in an upper portion of the trench above the shield electrode, wherein the gate electrode is insulated from the epitaxial layer by the first dielectric layer and insulated from the shield electrode by a second dielectric layer, wherein the first and second dielectric layers have the same thickness ranging between 10 to 25 nm; and

g) one or more source regions of the first conductivity type formed in a top surface of the body region, wherein each source region is adjacent a sidewall of the trench.

4. A shielded gate trench field effect transistor, comprising:

a) a substrate of a first conductivity type;

b) an epitaxial layer of the first conductivity type provided on top of the substrate;

c) a body region of a second conductivity type that is opposite to the first conductivity type formed above the epitaxial layer;

d) a trench formed in the body region and epitaxial layer, wherein the trench is lined with a first dielectric layer and wherein the trench is extended in depth about 0.5 microns or less;

e) a shield electrode formed in a lower portion of the trench, wherein the shield electrode is insulated from the epitaxial layer by the first dielectric layer;

f) a gate electrode formed in an upper portion of the trench above the shield electrode, wherein the gate electrode is insulated from the epitaxial layer by the first dielectric layer and insulated from the shield electrode by a second dielectric layer, wherein the first and second dielectric layers have the same thickness; and

g) one or more source regions of the first conductivity type formed in a top surface of the body region, wherein each source region is adjacent a sidewall of the trench.

5. The field effect transistor of claim 1 , wherein the epitaxial layer has a dopant concentration that is constant throughout its depth.

6. The field effect transistor of claim 1 , wherein the shield electrode is as wide as the gate electrode.

7. A shielded gate trench field effect transistor, comprising:

a) a substrate of a first conductivity type;

b) an epitaxial layer of the first conductivity type provided on top of the substrate;

c) a body region of a second conductivity type that is opposite to the first conductivity type formed above the epitaxial layer;

d) a trench formed in the body region and epitaxial layer, wherein the trench is lined with a first dielectric layer;

e) a shield electrode formed in a lower portion of the trench, wherein the shield electrode is insulated from the epitaxial layer by the first dielectric layer;

f) a gate electrode formed in an upper portion of the trench above the shield electrode, wherein the gate electrode is insulated from the epitaxial layer by the first dielectric layer and insulated from the shield electrode by a second dielectric layer, wherein the first and second dielectric layers have the same thickness; and

g) one or more source regions of the first conductivity type formed in a top surface of the body region, wherein each source region is adjacent a sidewall of the trench, wherein the shield electrode is an upside down T-shaped electrode with a horizontal portion and a vertical portion, and the gate electrode is split into two portions, each provided above the horizontal portion of the shield electrode.

8. The field effect transistor of claim 1 , further comprising a P column formed in a core cell connected to the body region at the surface or orthogonal to the core cell.

9. The field effect transistor of claim 1 , further comprising a source pad formed above the body region, wherein the source pad is electrically connected to the one or more source regions and insulated from the gate electrode and the shield electrode, the source pad providing an external contact to the one or more source region.

10. A shielded gate trench field effect transistor, comprising:

a) a substrate of a first conductivity type, wherein a drain pad is provided under the substrate;

b) an epitaxial layer of the first conductivity type provided on top of the substrate;

c) a body region of a second conductivity type that is opposite to the first conductivity type formed above the epitaxial layer;

d) a trench formed in the body region and epitaxial layer, wherein the trench is lined with a first dielectric layer;

e) a shield electrode formed in a lower portion of the trench, wherein the shield electrode is insulated from the epitaxial layer by the first dielectric layer;

f) a gate electrode formed in an upper portion of the trench above the shield electrode, wherein the gate electrode is insulated from the epitaxial layer by the first dielectric layer and insulated from the shield electrode by a second dielectric layer, wherein the first and second dielectric layers have the same thickness; and

g) one or more source regions of the first conductivity type formed in a top surface of the body region, wherein each source region is adjacent a sidewall of the trench.

11. A method for manufacturing a shielded gate trench field effect transistor, comprising:

a) providing an epitaxial layer of a first conductivity type on top of a substrate of the first conductivity type;

b) providing a body region of a second conductivity type above the epitaxial layer, wherein the second conductivity type is opposite to the first conductivity type;

c) providing a trench in the body region and epitaxial layer, wherein the trench is lined with a first dielectric layer and the trench has a pitch less than 1 μm;

d) providing a shield electrode in a lower portion of the trench, wherein the shield electrode is insulated from the epitaxial layer by the first dielectric layer;

e) providing a gate electrode in an upper portion of the trench above the shield electrode, wherein the gate electrode is insulated from the epitaxial layer by the first dielectric layer and insulated from the shield electrode by a second dielectric layer, wherein the first and second dielectric layers have the same thickness; and

f) providing one or more source regions of the first conductivity type in a top surface of the body region, wherein each source region is adjacent a sidewall of the trench.

12. The method of claim 11 , wherein the trench has a pitch about 0.6 um.

13. The method of claim 11 , wherein the thickness of the first and second dielectric layer is in a range between 10 to 25 nm.

14. The method of claim 11 , wherein the trench is extended in depth about 0.5 microns or less.

15. The method of claim 11 , wherein the epitaxial layer has a dopant concentration that is constant throughout its depth.

16. The method of claim 11 , wherein the shield electrode is as wide as the gate electrode.

17. The method of claim 11 , wherein the shield electrode is an upside down T-shaped electrode with a horizontal portion and a vertical portion, and the gate electrode is split into two portions, each provided above the horizontal portion of the shield electrode.

18. The method of claim 11 , further comprising forming a P column formed in a core cell connected to the body region at the surface or orthogonal to the core cell.