High performance interconnect physical layer
A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.
1. An apparatus comprising:
a receiver processor comprising an agent to support a layered protocol stack comprising physical layer logic, link layer logic, and protocol layer logic, wherein the agent is to:
receive a link layer data stream within an active link state (L0), wherein the link layer data comprises a set of flits;
intermittently enter a coordination link state (L0c), wherein the coordination link state defines a L0c interval in which physical layer control;
receive a control code within the L0c interval; and
initiate a reset of the link based on a control code mismatch, wherein the control code mismatch is based on an identification that the control code fails to match one of a set of specified codes.
2. The apparatus of claim 1 , wherein the control code mismatch is based on a bit error.
3. The apparatus of claim 1 , wherein the physical layer logic is further to attempt to resolve the bit error and the control code mismatch is identified in response to a failure to resolve the bit error.
4. The apparatus of claim 1 , wherein the control code is to be from a set comprising a reset request code, a low power entry request, a partial width entry request, and a partial width exit request.
5. The apparatus of claim 1 , wherein the L0c interval is to be entered according to a defined interval.
6. The apparatus of claim 5 , wherein the L0c interval is to be entered periodically according to the defined interval.
7. The apparatus of claim 1 , wherein the L0c interval is a defined length.
8. The apparatus of claim 1 , wherein the L0c interval is to begin and end on clean flit boundaries.
9. The apparatus of claim 1 , wherein the control code comprises an 8-bit code.
10. The apparatus of claim 1 , wherein the control code comprises a request control sequence.
11. The apparatus of claim 1 , wherein the agent is further to detect that the control code fails to match one of a set of specified codes.
12. The apparatus of claim 11 , wherein the agent comprises comparison circuitry to detect that the control code fails to match one of the set of specified codes.
13. The apparatus of claim 1 , further comprising transmitter logic to send data to indicate entry into L0c, and send one or more control codes within L0c intervals.
14. The apparatus of claim 1 , wherein the reset comprises an in-band reset.
15. A method comprising:
receiving a link layer data stream within an active link state (L0), wherein the link layer data comprises a set of flits;
intermittently entering a coordination link state (L0c), wherein the coordination link state defines a L0c interval in which physical layer control;
receiving a control code within the L0c interval; and
initiating a reset of the link based on a control code mismatch, wherein the control code mismatch is based on an identification that the control code fails to match one of a set of specified codes.
16. The method of claim 15 , further comprising sending one or more control codes within the L0c interval.
17. The method of claim 15 , further comprising detecting that the control code fails to match one of the set of specified codes.
18. A system comprising:
a first computing device; and
a second computing device coupled to the first computing device by a link, wherein the second processor device comprises:
link layer circuitry to receive a link layer data stream within an active link state (L0), wherein the link layer data comprises a set of flits;
state machine logic to intermittently enter a coordination link state (L0c), wherein the coordination link state defines a L0c interval in which physical layer control;
physical layer circuitry to:
identify a control code received from the first computing device within the L0c interval; and
initiate a reset of the link based on a control code mismatch, wherein the control code mismatch is based on an identification that the control code fails to match one of a set of specified codes.
19. The system of claim 18 , wherein the first computing device comprises a first processor and the second computing device comprises a second processor.