Display apparatus and method of driving the same

1. A display apparatus comprising:

a display panel comprising first through m-th fan-out lines, first through m-th data lines, a first dummy line, and a second dummy line, wherein the first through m-th fan-out lines are sequentially disposed along a first direction, wherein the first through m-th data lines are sequentially disposed along the first direction, wherein the first through m-th data lines are connected to the first through m-th fan-out lines at first through m-th nodes, respectively, wherein the first dummy line is connected to only an n-th node, wherein the second dummy line is connected to an (n+1)-th node, and wherein m and n are positive integers and m is greater than n;

a first data driver configured to output first through n-th data voltages to the first through n-th fan-out lines, respectively, based on a data signal;

a second data driver configured to output (n+1)-th through m-th data voltages to the (n+1)-th through m-th fan-out lines, respectively, based on the data signal; and

a timing controller configured to compensate the data signal based on a voltage of the n-th node and a voltage of the (n+1)-th node.

2. The display apparatus of claim 1 , wherein the timing controller is configured to obtain a voltage of the n-th node through the first dummy line and the timing controller is configured to obtain a voltage of the (n+1)-th node through the second dummy line.

3. The display apparatus of claim 1 , wherein the timing controller is configured to compare a voltage of the n-th node with a voltage of the (n+1)-th node.

4. The display apparatus of claim 3 , wherein the timing controller is configured to compensate the data signal so that the voltage of the n-th node is substantially the same as the voltage of the (n+1)-th node.

5. The display apparatus of claim 1 , wherein the timing controller is configured to compare a voltage of the n-th node and a voltage of the (n+1)-th node with a reference voltage.

6. The display apparatus of claim 5 , wherein the timing controller is configured to compensate the data signal so that the voltage of the n-th node and the voltage of the (n+1)-th node are substantially the same as the reference voltage.

7. The display apparatus of claim 5 , wherein the reference voltage is substantially the same as either the n-th data voltage or the (n+1)-th data voltage.

8. The display apparatus of claim 1 , wherein the timing controller is configured to compensate n-th and (n+1)-th data corresponding to the n-th and (n+1)-th data lines.

9. The display apparatus of claim 8 , wherein the timing controller is configured to compensate first through (n−1)-th and (n+2)-th through m-th data corresponding to the first through (n−1)-th and (n+2)-th through m-th data lines, respectively, in order of closeness to the n-th and (n+1)-th data lines, after first compensating the n-th and (n+1)-th data.

10. The display apparatus of claim 1 , wherein the first and second data drivers are configured to output compensated first through m-th data voltages to the first through m-th fan-out lines, respectively, based on the compensated data signal.

11. The display apparatus of claim 1 , wherein the first and second dummy lines are both disposed between the n-th fan-out line and the (n+1)-th fan-out line.

12. A method of driving a display apparatus, the method comprising:

outputting first through n-th data voltages to first ends of first through n-th fan-out lines, respectively, based on a data signal, wherein n is a positive integer;

outputting (n+1)-th through m-th data voltages to first ends of (n+1)-th through m-th fan-out lines, respectively, based on the data signal, wherein m is a positive integer greater than n;

obtaining an n-th voltage of a second end of the n-th fan-out line through a first dummy line;

obtaining an (n+1)-th voltage of a second end of the (n+11)-th fan-out line through a second dummy line; and

compensating the data signal based on the n-th and (n+1)-th voltages,

wherein compensating the data signal comprises compensating a data signal corresponding to the n-th and (n+1)-th fan-out lines, and

wherein the first through m-th fan-out lines are sequentially disposed along a first direction, and wherein compensating the data signal comprises: compensating a data signal corresponding to the first through (n−1)-th fan-out lines in order of closeness to the n-th fan-out lines, and compensating a data signal corresponding to the (n+2)-th through m-th fan-out lines in order of closeness to the (n+1)-th fan-out lines.

13. The method of claim 12 , wherein compensating the data signal comprises: comparing the n-th voltage with the (n+1)-th voltage.

14. The method of claim 13 , wherein compensating the data signal further comprises: compensating the data signal so that the n-th voltage is substantially equal to the (n+1)-th voltage.

15. The method of claim 12 , wherein compensating the data signal comprises: comparing the n-th and (n+1)-th voltages with a reference voltage.

16. The method of claim 15 , wherein compensating the data signal further comprises: compensating the data signal so that the n-th voltage and the (n+1)-th voltage are each substantially equal to the reference voltage.

17. The method of claim 12 , further comprising: outputting compensated first through m-th data voltages to the first ends of the first through m-th fan-out lines based on the compensated data signal.

18. A display apparatus, compromising:

a display panel including a first display area and a second display area;

a first data driver for driving the first display area;

a second data driver for driving the second display area;

a first set of fan-out lines connected to the first data driver;

a first set of data lines connected to the first set of fan-out lines and running down the first display area;

a second set of fan-out lines connected to the second data driver;

a second set of data lines connected to the second set of fan-out lines and running down the second display area;

a first dummy line disposed between the first set of fan-out lines and the second set of fan-out lines such that the entirety of the first set of fan-out lines is on a first side of the first dummy line and the entirety of the second set of fan-out lines is on a second side of the first dummy line that is opposite to the first side of the first dummy line; and

a second dummy line disposed between the first set of fan-out lines and the second set of fan-out lines such that the entirety of the first set of fan-out lines is on a first side of the second dummy line and the entirety of the second set of fan-out lines is on a second side of the second dummy line that is opposite to the first side of the second dummy line,

wherein the first data driver provides a first data signal to the first set of fan-out lines and a first reference signal to the first dummy line, and the second data driver provides a second data signal to the second set of fan-out lines and a second reference signal to the second dummy line.