Control of current collapse in thin patterned GaN
A GaN device is formed on a semiconductor substrate having a plurality of recessed regions formed in a surface thereof. A seed layer, optional buffer layer, and gallium nitride layer such as a carbon-doped gallium nitride layer are successively deposited within the recessed regions. Improved current collapse response of the GaN device is attributed to maximum length and width dimensions of the multilayer stack.
1. A semiconductor device comprising:
a substrate having a recessed region disposed in a surface thereof, the recessed region includes a first vertical sidewall of the substrate, a second vertical sidewall of the substrate, and a horizontal surface of a semiconductor material of the substrate;
a seed layer disposed within the recessed region and directly on the horizontal surface of the semiconductor material, wherein the seed layer extends continuously from the first vertical sidewall to the second vertical sidewall of the recess region; and
a layered structure disposed on the seed layer, the layered structure comprising a buffer layer and a gallium nitride layer, wherein the buffer layer is present directly on a topmost surface of the seed layer and extends continuously from the first vertical sidewall to the second vertical sidewall, and wherein the seed layer and the layered structure have outermost vertical sidewalls that are vertically aligned to each other, wherein the first and second vertical sidewalls include a sidewall of a dielectric material and a sidewall of a topmost semiconductor layer, the sidewall of the dielectric material is between the sidewall of the topmost semiconductor layer and the horizontal surface of the semiconductor material of the substrate.
2. The device of claim 1 , wherein the layered structure has a length of 10 to 50 microns and a width of 10 to 50 microns.
3. The device of claim 1 , wherein the layered structure has a thickness of at least 1 micron.
4. The device of claim 1 , wherein the layered structure has a thickness of 0.5 to 2.5 microns.
5. The device of claim 1 , wherein the buffer layer comprises AlGaN and the gallium nitride layer comprises carbon doped GaN.
6. The device of claim 1 , wherein the buffer layer has a thickness of 0 to 1000 nm and the gallium nitride layer has a thickness of 500 to 1500 nm.
7. The device of claim 1 , wherein the substrate has a diameter of at least 50 mm and a thickness of 725 to 775 microns.
8. The device of claim 1 , wherein the substrate is a semiconductor-on-insulator substrate.
9. The device of claim 1 , wherein the first and second vertical sidewalls include a portion of the semiconductor material.
10. The device of claim 1 , wherein the device has a current collapse of less than 10%.
11. The device of claim 1 , wherein the device is a gallium nitride high electron mobility transistor.
12. The device of claim 1 , wherein the recessed region has a depth of 0.6 to 3.5 microns.
13. The device of claim 1 , wherein the substrate has a bow of less than 500 microns.
14. A semiconductor device comprising:
a substrate having a recessed region disposed in a surface thereof, the recessed region includes a first vertical sidewall of the substrate, a second vertical sidewall of the substrate, and a horizontal surface of a semiconductor material of the substrate;
a seed layer disposed within the recessed region and directly on the horizontal surface of the semiconductor material, wherein the seed layer extends continuously from the first vertical sidewall to the second vertical sidewall; and
a structure comprising a gallium nitride layer located directly on a topmost surface of the seed layer, wherein gallium nitride layer extends continuously from, and is in direct contact with, the first vertical sidewall to the second vertical sidewall, and wherein the seed layer and the gallium nitride layer have outermost vertical sidewalls that are vertically aligned to each other, wherein the first and second vertical sidewalls include a sidewall of a dielectric material and a sidewall of a topmost semiconductor layer, the sidewall of the dielectric material is between the sidewall of the topmost semiconductor layer and the horizontal surface of the semiconductor material of the substrate.
15. The device of claim 14 , wherein the structure has a thickness of at least 0.5 microns, a length of 1 to 200 microns, and a width of 1 to 200 microns.
16. The device of claim 1 , wherein the layered structure has a thickness of at least 0.5 microns, a length of 1 to 200 microns, and a width of 1 to 200 microns.