Dual-sided memory module with channels aligned in opposition

1. A memory module comprising:

a circuit board;

at least four first packages mounted on a first side of the circuit board, each first package including a separate single channel and four ranks; and

at least four second packages mounted on a second side of the circuit board directly opposite the four first packages, each second package including separate single channel and four ranks;

wherein the circuit board further comprises four package area interconnects electrically connecting the four first packages to the four second packages, each of the package area interconnects comprising:

a first plurality of interconnects electrically connecting power landing pads on the first side of the circuit board to power landing pads on the second side of the circuit board; and

a second plurality of interconnects electrically connecting power and signal landing pads on the first side of the circuit board to power and signal landing pads on the second side of the circuit board;

wherein the second plurality of interconnects is greater than the first plurality of interconnects.

2. The memory module of claim 1 , wherein each first package and each second package comprises 8 GB of memory.

3. The memory module of claim 2 , wherein each first package and each second package comprises eight 8 Gb dice, with two 8 Gb dice per rank.

4. The memory module of claim 3 , wherein each channel comprises 16 bits.

5. The memory module of claim 1 , wherein each first package and each second package comprises 16 GB of memory.

6. The memory module of claim 5 , wherein each first package and each second package comprises eight 16 Gb dice, with two 8 Gb dice per rank.

7. A memory module comprising:

a circuit board;

a first memory package mounted on a first side of the circuit board, the first memory packaging including:

a first terminal section including first power terminals and first signal terminals to operate a first plurality of memory banks contained within the first memory package; and

a second terminal section including second power terminals to operate the first plurality of memory banks; and

a second memory package mounted on a second side of the circuit board opposite the first side, the second memory package including:

a third terminal section including third power terminals and second signal terminals to operate a second plurality of memory banks contained within the second memory package; and

a fourth terminal section including fourth power terminals to operate the second plurality of memory banks;

wherein the circuit board includes a section of interconnects that electrically connect the first power terminals with the fourth power terminals, and electrically connect the second power terminals with the third power terminals.

8. The memory module of claim 7 , wherein:

the first terminal section is bonded to a first landing pad section on the first side of the circuit board;

the second terminal section is bonded to a second landing pad section on the first side of the circuit board, wherein the second landing pad section includes more landing pads than the second terminal section includes electrically functional terminals;

the third terminal section is bonded to a third landing pad section on the second side of the circuit board; and

the fourth terminal section is bonded to a fourth landing pad section on the second side of the circuit board.

9. The memory module of claim 8 , wherein the third landing pad section includes more electrically functional landing pads than the fourth landing pad section.

10. The memory module of claim 8 , wherein the second landing pad section includes second signal pads and second power pads, and the third landing pad section includes third signal pads and third power pads, and the plurality of interconnects electrically connect the second signal pads with the third signal pads, and the second power pads with the third power pads.

11. The memory module of claim 10 , wherein the second signal pads are not operably coupled with the second terminal section of the first package.

12. A memory package comprising:

a plurality of memory banks arranged in at least two ranks;

a first terminal section including first power terminals and first signal terminals to operate the plurality of memory banks; and

a second terminal section including second power terminals to operate the plurality of memory banks;

wherein the first terminal section includes a larger number of total electrically functional terminals and total signal terminals than the second terminal section.

13. The memory package of claim 12 , wherein the first signal terminals comprise a single channel.

14. The memory package of claim 13 , wherein the plurality of memory banks comprises 8 GB of memory.

15. The memory package of claim 14 , wherein the plurality of memory banks comprises eight 8 Gb dice, with two 8 Gb dice per rank.

16. The memory package of claim 15 , wherein the single channel is a 16 bit channel.

17. The memory package of claim 13 , wherein the plurality of memory banks comprises 16 GB of memory.

18. The memory package of claim 17 , wherein the plurality of memory banks comprises eight 16 Gb dice, with two 8 Gb dice per rank.

19. The memory package of claim 13 , wherein the plurality of memory banks is arranged in at least four ranks.

20. The memory package of claim 19 , wherein the second terminal section additionally comprises a clock enable terminal and a chip select terminal, each of which is not included in the first terminal section.

21. A circuit board comprising:

a first side including a first package landing area including a first landing pad section and a second landing pad section;

a second side opposite the first side, the second side including a second package landing area including a third landing pad section opposite the second landing pad section and a fourth landing pad section opposite the first landing pad section;

a first plurality of interconnects electrically connecting power landing pads contained in the first landing pad section and the fourth landing pad section; and

a second plurality of interconnects electrically connecting power landing pads and signal landing pads contained in the second landing pad section and the third landing pad section;

wherein the second plurality of interconnects is greater than the first plurality of interconnects.

22. The circuit board of claim 21 , wherein the fourth landing pad section includes fewer signal landing pads than each of the first, second, and third landing pad section.

23. The circuit board of claim 22 , wherein the third landing pad section is a substantial mirror image of the first landing pad section.

24. A memory module comprising:

a circuit board comprising:

a first side including a first package landing area including a first landing pad section and a second landing pad section;

a second side opposite the first side, the second side including a second package landing area including a third landing pad section opposite the second landing pad section and a fourth landing pad section opposite the first landing pad section;

a first plurality of interconnects electrically connecting power landing pads contained in the first landing pad section and the fourth landing pad section; and

a second plurality of interconnects electrically connecting power landing pads and signal landing pads contained in the second landing pad section and the third landing pad section; and

a memory package mounted onto the first and second landing pad sections, the memory package comprising two ranks, a first channel electrically coupled with the first landing pad section, and a second channel electrically coupled with the second landing pad section;

wherein a package is not bonded to the third landing pad section and the fourth landing pad section.