Semiconductor device and method of manufacturing the same
The embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first III-V compound layer disposed over a substrate and a second III-V compound layer disposed over the first III-V compound layer, wherein a first carrier channel is formed in the interface between the first III-V compound layer and the second III-V compound layer. The semiconductor device also includes a third III-V compound layer disposed over the second III-V compound layer and a fourth III-V compound layer disposed over the third III-V compound layer, wherein a second carrier channel is formed in an interface between the third III-V compound layer and the fourth III-V compound layer. The semiconductor device includes a gate structure and S/D regions disposed on two opposite sides of the gate structure, wherein the first carrier channel and the second carrier channel are extended between the S/D regions.
1. A semiconductor device, comprising:
a substrate;
a first III-V compound layer disposed over the substrate;
a second III-V compound layer disposed over the first III-V compound layer, wherein a first carrier channel is formed in an interface between the first III-V compound layer and the second III-V compound layer;
a third III-V compound layer disposed over the second III-V compound layer;
a fourth III-V compound layer disposed over the third III-V compound layer, wherein a second carrier channel is formed in an interface between the third III-V compound layer and the fourth III-V compound layer;
a gate structure disposed over the fourth III-V compound layer;
a source region and a drain region disposed on two opposite sides of the gate structure, wherein the first carrier channel and the second carrier channel are extended between the source region and the drain region; and
a first extended electrode disposed between the second III-V compound layer and the third III-V compound layer.
2. The semiconductor device as claimed in claim 1 , wherein the first III-V compound layer and the third III-V compound layer comprise GaN, the second III-V compound layer and the fourth III-V compound layer comprise Al x Ga 1-x N, and 0<x<1.
3. The semiconductor device as claimed in claim 2 , wherein a composition of the second III-V compound layer is the same as that of the fourth III-V compound layer.
4. The semiconductor device as claimed in claim 2 , wherein a composition of the second III-V compound layer is different from that of the fourth III-V compound layer.
5. The semiconductor device as claimed in claim 1 , further comprising:
a second extended electrode disposed between the fourth III-V compound layer and the gate structure, wherein the first extended electrode and the second electrode are electrically connected to the gate structure.
6. The semiconductor device as claimed in claim 5 , wherein the first extended electrode and the second extended electrode comprise a p-type doped III-V compound or a metal.
7. The semiconductor device as claimed in claim 6 , wherein the first extended electrode and the second extended electrode comprise a p-type doped GaN.
8. The semiconductor device as claimed in claim 5 , further comprising:
a conductive wire disposed in the substrate, and electrically connected to the first extended electrode, the second extended electrode and the gate structure.
9. The semiconductor device as claimed in claim 5 , wherein the first extended electrode and the second extended electrode are located directly under the gate structure.
10. The semiconductor device as claimed in claim 5 , wherein the first extended electrode is surrounded by the second III-V compound layer, and the second extended electrode is surrounded by the fourth III-V compound layer.
11. The semiconductor device as claimed in claim 5 , wherein a portion of the fourth III-V compound layer is disposed between the second extended electrode and the third III-V compound layer, and a portion of the second III-V compound layer is disposed between the first extended electrode and the first III-V compound layer.
12. The semiconductor device as claimed in claim 5 , further comprising:
a protective layer disposed on a surface of the fourth III-V compound layer, wherein the protective layer comprises GaN or SiN.
13. The semiconductor device as claimed in claim 5 , wherein there is no carrier channel formed between the second III-V compound layer and the third III-V compound layer.
14. A method for forming a semiconductor device, comprising:
providing a substrate;
forming a first III-V compound layer in the substrate;
forming a second III-V compound layer over the first III-V compound layer so that a first carrier channel is formed in an interface between the first III-V compound layer and the second III-V compound layer;
forming a third III-V compound layer over the second III-V compound layer;
forming a first extended electrode between the second III-V compound layer and the third III-V compound layer;
forming a fourth III-V compound layer over the third III-V compound layer so that a second carrier channel is formed in an interface between the third III-V compound layer and the fourth III-V compound layer;
forming a gate structure over the fourth III-V compound layer; and
forming a source region and a second region on two opposite sides of the gate structure, and the source region and the drain region penetrate the fourth III-V compound layer, the third III-V compound layer, and the second III-V compound layer, wherein the first carrier channel and the second carrier channel are extended between the source region and the drain region.
15. The method as claimed in claim 14 , wherein the first III-V compound layer and the third III-V compound layer comprise GaN, the second III-V compound layer and the fourth III-V compound layer comprise Al x Ga 1-x N, and 0<x<1.
16. The method as claimed in claim 14 , further comprising:
forming a second extended electrode between the fourth III-V compound layer and the gate structure, wherein the first extended electrode and the second extended electrode are electrically connected to the gate structure, and the first extended electrode and the second extended electrode comprise a p-type doped III-V compound or a metal.
17. The method as claimed in claim 16 , wherein the first extended electrode and the second extended electrode comprise a p-type doped GaN.
18. The method as claimed in claim 16 , further comprising:
forming a conductive wire in the substrate so that the first extended electrode and the second extended electrode are electrically connected to the gate structure.
19. The method as claimed in claim 14 , further comprising:
forming a protective layer on a surface of the fourth III-V compound layer, wherein the protective layer comprises GaN or SiN.
20. The method as claimed in claim 14 , wherein there is no carrier channel formed between the second III-V compound layer and the third III-V compound layer.