Gallium nitride superjunction transistor
Techniques to increase the number of current paths (or “channels”) in a GaN transistor, without increasing the device area, thereby decreasing the on-resistance. In addition, this disclosure describes techniques to utilize back-side field management to improve the device's performance. For example, the techniques can include using p-type implantation into the substrate, e.g., silicon carbide (SiC), as a field management tool to form a superjunction device, thereby increasing the effective field and reducing the on-resistance multiplied by the output charge (Qoss).
1 . A compound semiconductor heterostructure transistor device having multiple two-dimensional electron gas channels, the compound semiconductor heterostructure transistor device comprising:
a substrate;
a first semiconductor material layer formed over the substrate;
a second semiconductor material layer formed over the first semiconductor material to form a first compound semiconductor heterostructure having a buried first two-dimensional electron gas (2DEG) channel, wherein the buried first 2DEG channel is more electrically conductive than either the first semiconductor material layer or the second semiconductor material layer;
a third semiconductor material layer formed over a fourth semiconductor material layer, wherein the fourth semiconductor material layer is formed over the substrate, to form a second compound semiconductor heterostructure having a topside second 2DEG channel, wherein the topside second 2DEG channel is more electrically conductive than either the third semiconductor material layer or the fourth semiconductor material layer;
a drain electrode electrically coupled to the first semiconductor material layer;
a source electrode electrically coupled to the topside second 2DEG channel; and
a gate electrode formed over the third semiconductor material layer, wherein the gate electrode is associated with only the topside second 2DEG channel and not associated with the buried first 2DEG channel; and
a conductive material extending vertically and electrically coupling 1) the buried first 2DEG channel and 2) the topside second 2DEG channel, wherein a current through the buried first 2DEG channel is approximately the same as a current through the topside second 2DEG channel.
2 . The compound semiconductor heterostructure transistor device of claim 1 , comprising:
a first doped semiconductor material extending vertically between and electrically coupling the second semiconductor material layer and the third semiconductor material layer.
3 . The compound semiconductor heterostructure transistor device of claim 2 , wherein the gate electrode is a first gate electrode, wherein the first gate electrode is positioned between the source electrode and the drain electrode and positioned adjacent a first side of the source electrode, the compound semiconductor heterostructure transistor device further comprising:
a second gate electrode positioned adjacent a second side of the source electrode; and
a conductive material extending vertically between and electrically coupling the buried first 2DEG channel and the topside second 2DEG channel.
4 . The compound semiconductor heterostructure transistor device of claim 1 , wherein the third semiconductor material layer underlies completely between the source electrode and the drain electrode.
5 . The compound semiconductor heterostructure transistor device of claim 4 , wherein the gate electrode is a first gate electrode, wherein the first gate electrode is positioned between the source electrode and the drain electrode and positioned adjacent a first side of the source electrode, the compound semiconductor heterostructure transistor device further comprising:
a second gate electrode positioned adjacent a second side of the source electrode;
a conductive material extending vertically between and electrically coupling the second semiconductor material layer and the third semiconductor material layer.
6 . The compound semiconductor heterostructure transistor device of claim 5 , further comprising:
a field plate formed over the third semiconductor material layer.
7 . The compound semiconductor heterostructure transistor device of claim 1 , wherein the third semiconductor material layer does not underlie completely between the source electrode and the drain electrode.
8 . The compound semiconductor heterostructure transistor device of claim 7 , wherein the source electrode is positioned between the gate electrode and the drain electrode, the compound semiconductor heterostructure transistor device further comprising:
a fifth semiconductor material layer formed over the second semiconductor material layer and a sixth semiconductor material layer formed over the fifth semiconductor material layer to form a third compound semiconductor heterostructure having a buried third 2DEG channel, wherein the buried third 2DEG channel is more electrically conductive than either the fifth semiconductor material layer or the sixth semiconductor material layer; and
wherein the conductive material extending extends vertically and electrically couples coupling 1) the buried first 2DEG channel and 2) the buried third 2DEG channel, and 3) the topside second 2DEG channel with the 3) the buried third 2DEG channel.
9 . The compound semiconductor heterostructure transistor device of claim 8 , wherein the substrate includes silicon, the compound semiconductor heterostructure transistor device further comprising:
a metal field plate positioned between the source electrode and the drain electrode and positioned above the fourth semiconductor material layer.
10 . The compound semiconductor heterostructure transistor device of claim 1 , comprising:
a dopant layer implanted in the substrate, wherein the dopant layer includes a p-type material forming a first region.
11 . The compound semiconductor heterostructure transistor device of claim 10 , wherein the dopant layer further includes an n-type material forming a second region, wherein the first region is adjacent the second region, and wherein the first region and the second region form a p-n junction diode.
12 . The compound semiconductor heterostructure transistor device of claim 1 , wherein the substrate includes silicon carbide.
13 . A method of forming a compound semiconductor heterostructure transistor device, the method comprising:
forming a first semiconductor material layer over a substrate;
forming a second semiconductor material layer over the first semiconductor material layer to form a first compound semiconductor heterostructure having a buried first two-dimensional electron gas (2DEG) channel, wherein the buried first 2DEG channel is more electrically conductive than either the first semiconductor material layer or the second semiconductor material layer;
forming a third semiconductor material layer over a fourth semiconductor material layer, wherein the fourth semiconductor material layer is formed over the substrate, to form a second compound semiconductor heterostructure having a topside second 2DEG channel, wherein the topside second 2DEG channel is more electrically conductive than either the third semiconductor material layer or the fourth semiconductor material layer;
forming a drain electrode electrically coupled to the first semiconductor material layer;
forming a source electrode electrically coupled to only the topside second 2DEG channel; and
forming a gate electrode over the third semiconductor material layer; and
forming a conductive material that extends vertically and electrically couples 1) the buried first 2DEG channel and 2) the topside second 2DEG channel, wherein a current through the buried first 2DEG channel is approximately the same as a current through the topside second 2DEG channel.
14 . The method of claim 13 , comprising:
forming a first doped semiconductor material that extends vertically between and electrically couples the second semiconductor material layer and the third semiconductor material layer.
15 . The method of claim 14 , wherein the gate electrode is a first gate electrode, wherein the first gate electrode is positioned between the source electrode and the drain electrode and positioned adjacent a first side of the source electrode, the method further comprising:
forming a second gate electrode positioned adjacent a second side of the source electrode; and
forming a conductive material that extends vertically between and electrically couples the buried first 2DEG channel and the topside second 2DEG channel.
16 . The method of claim 14 , further comprising:
forming a field plate over the third semiconductor material layer.
17 . The method of claim 13 , further comprising:
forming a fifth semiconductor material layer over the second semiconductor material layer;
forming a sixth semiconductor material layer formed over the fifth semiconductor material layer to form a third compound semiconductor heterostructure having a buried third 2DEG channel, wherein the buried third 2DEG channel is more electrically conductive than either the fifth semiconductor material layer or the sixth semiconductor material layer; and
wherein the forming a conductive material that extends vertically between and electrically couples the 1) buried first 2DEG channel and the buried third 2DEG channel, and 2) the topside second 2DEG channel with the 3) the buried third 2DEG channel.
18 . The method of claim 17 , further comprising:
etching away a portion of the fourth semiconductor material layer, the fifth semiconductor material layer, second semiconductor material layer, and the third semiconductor material layer, wherein the etched-away portion is positioned between the source electrode and the drain electrode and positioned above the fourth semiconductor material layer; and
forming a metal field plate over the etched-away portion.