Memory control apparatus and memory control method
A memory control apparatus including: a writing unit configured to output a write request for writing to a memory and issues a first event every time a write operation of each of the first blocks is completed; a reading unit configured to output a readout request for reading of image data that has been written to the memory by the writing unit and issues a second event every time a readout operation of the second block is completed; and a controller that performs a process of incrementing a count value in response to the first event, performs a process of decrementing the count value in response to the second event, and controls whether to permit the write request and the readout request, respectively, based on the count value.
1. A memory control apparatus comprising:
a writing unit configured to output a write request for writing to a memory and, in response to the write request being permitted, write image data to the memory, wherein a plurality of first blocks are included in one frame of image data to be written to the memory by the writing unit, and the writing unit issues a first event every time a write operation of each of the first blocks is completed;
a reading unit configured to output a readout request for reading of image data that has been written to the memory by the writing unit and, in response to the readout request being permitted, read out the image data from the memory, wherein, while image data of one frame is being written in the memory by the writing unit, the reading unit outputs a readout request for the image data of the one frame written to the memory, a second block is included in one frame of the image data read out from the memory by the reading unit, and the reading unit issues a second event every time a readout operation of the second block is completed; and
a controller configured to control whether to permit the write request and the readout request respectively, wherein the controller performs a process of incrementing a count value by a first value based on the number of the second blocks in a horizontal direction included in the one frame in response to the first event, the controller performs a process of decrementing the count value by a second value based on the number of the first blocks in the horizontal direction included in the one frame in response to the second event, the controller does not permit the write request in a case where the count value is larger than a first threshold, and the controller does not permit the readout request in a case where the count value is smaller than a second threshold.
2. The memory control apparatus according to claim 1 , wherein
the controller sets
the second threshold based on a difference between the number of the first blocks in the horizontal direction included in the one frame and the number of the second blocks in the horizontal direction included in the one frame.
3. The memory control apparatus according to claim 1 , wherein the controller has a first comparator that compares the count value with the first threshold, a second comparator that compares the count value with the second threshold, a first mask unit that controls whether to mask a write request from the writing unit in accordance with a comparison result by the first comparator, and a second mask unit that controls whether or not to mask a readout request from the reading unit in accordance with a comparison result by the second comparator.
4. The memory control apparatus according to claim 1 , wherein
the writing unit issues the first event in response to a write address reaching a final address of each of the first blocks, and
the reading unit issues the second event in response to a readout address reaching a final address of the second block.
5. The memory control apparatus according to claim 1 , wherein the controller sets the count value to an initial value in response to completion of readout of the image data of one frame performed by the reading unit.
6. The memory control apparatus according to claim 5 , wherein
the first blocks and the second block are defined by dividing one frame of image data, respectively, and
the initial value is set in accordance with forms of divisions of the first blocks and the second block.
7. The memory control apparatus according to claim 1 , wherein
the writing unit writes the plurality of first blocks of one frame to the memory in a first predetermined order, and
the reading unit reads out the plurality of second blocks of one frame from the memory in a second predetermined order which corresponds to the first predetermined order.
8. The memory control apparatus according to claim 1 , wherein a size of each of the first blocks is different from a size of the second block.
9. The memory control apparatus according to claim 1 , wherein the first blocks and the second block are any one of a minimum access unit, a row including a plurality of minimum access units, a division block defined by dividing one frame in a horizontal direction and a vertical direction, a block row including a plurality of the divided blocks neighboring in the horizontal direction, and one frame, respectively.
10. A memory control method comprising:
outputting a write request for writing to a memory and, in response to the write request being permitted, writing image data to the memory, wherein a plurality of first blocks are included in one frame of image data to be written to the memory, and a first event is issued every time a write operation of each of the first blocks is completed;
outputting a readout request for reading of image data that has been written to the memory and, in response to the readout request being permitted, reading out the image data from the memory, wherein, while image data of one frame is being written to the memory, a readout request for image data of the one frame written to the memory is output, a second block is included in one frame of the image data read out from the memory, and a second event is issued every time a readout operation of the second block is completed; and
controlling whether to permit the write request and the readout request respectively, wherein a process of incrementing a count value by a first value based on the number of the second blocks in a horizontal direction included in the one frame is performed in response to the first event, a process of decrementing the count value by a second value based on the number of the first blocks in the horizontal direction included in the one frame is performed in response to the second event, the write request is not permitted in a case where the count value is larger than a first threshold, and the readout request is not permitted in a case where the count value is smaller than a second threshold.
11. The memory control apparatus according to claim 1 , wherein
the second threshold is a value which is obtained by multiplying a difference between the number of the second blocks in the horizontal direction included in the one frame and the number of the second blocks in the horizontal direction included in two frames, the number of the first blocks in the horizontal direction included in the one frame, and the number of the second blocks in the horizontal direction included in the one frame, and
the first threshold is a value which is larger than the second threshold, by an amount corresponding to a value obtained by adding a horizontal division number of the first blocks and a horizontal division number of the second blocks.