Memory affinity management

1. A computer-implemented method for memory affinity management in a shared pool of configurable computing resources that utilizes non-uniform memory access (NUMA), the method comprising:

monitoring an access relationship between a set of hardware memory components and a set of software assets;

storing a set of memory affinity data which indicates the access relationship between the set of software assets and the set of hardware memory components;

monitoring, using a hardware unit which is coupled with a hardware processor component, the access relationship between the set of hardware memory components and a set of containers which utilizes an operating-system-level virtualization technique;

structuring the hardware unit to include a hardware processor performance monitoring unit (PMU);

configuring the hardware processor PMU to monitor a set of events corresponding to the access relationship between the set of hardware memory components and the set of containers which utilizes the operating-system-level virtualization technique;

determining, using the set of memory affinity data, a NUMA utilization configuration with respect to the set of software assets;

executing, based on the NUMA utilization configuration, a set of accesses pertaining to the set of software assets and the set of hardware memory components;

storing, in a special purpose register by the hardware unit, the set of memory affinity data which indicates the access relationship between the set of hardware memory components and the set of containers which utilizes the operating-system-level virtualization technique;

tracking, using a set of identifiers related to the set of containers which utilizes the operating-system-level virtualization technique, the set of events corresponding to the access relationship between the set of hardware memory components and the set of containers which utilizes the operating-system-level virtualization technique;

configuring the set of identifiers to indicate both a set of hardware chips related to the set of containers and the set of containers, wherein a respective identifier indicates both a respective hardware chip related to a respective software asset and a respective container which utilizes the operating-system-level virtualization technique;

collecting, based on the set of events, the set of memory affinity data;

normalizing the set of memory affinity data to determine the NUMA utilization configuration with respect to the set of software assets;

weighting the set of memory affinity data to determine the NUMA utilization configuration with respect to the set of software assets;

determining, using the set of memory affinity data based on and in response to both normalizing the set of memory affinity data and weighting the set of memory affinity data, the NUMA utilization configuration with respect to the set of containers which utilizes the operating-system-level virtualization technique;

receiving a new access request from an individual hardware processor of a set of hardware processors;

identifying the individual hardware processor of the set of hardware processors;

executing, based on the NUMA utilization configuration, the new access request pertaining to the set of containers and the set of hardware memory components; and

logging, pertaining to the set of memory affinity data, the new access request.

2. The method of claim 1 , further comprising:

monitoring the access relationship between the set of hardware memory components and a set of containers which utilizes an operating-system-level virtualization technique;

storing the set of memory affinity data which indicates the access relationship between the set of containers and the set of hardware memory components;

determining, using the set of memory affinity data, the NUMA utilization configuration with respect to the set of containers which utilizes the operating-system-level virtualization technique; and

executing, based on the NUMA utilization configuration, the set of accesses pertaining to the set of software assets and the set of hardware memory components.

3. The method of claim 1 , further comprising:

tracking, using a set of identifiers related to the set of software assets, a set of events corresponding to the access relationship between the set of software assets and the set of hardware memory components.

4. The method of claim 3 , further comprising:

detecting a set of cache misses;

ascertaining, based on and in response to detecting the set of cache misses, a respective identifier of the set of identifiers which

relates to a respective software asset of the set of software assets, and

corresponds to the set of cache misses; and

collecting, using the set of cache misses, the set of memory affinity data.

5. The method of claim 3 , further comprising:

detecting a set of memory accesses; and

ascertaining, based on and in response to detecting the set of memory accesses, a respective identifier of the set of identifiers which

relates to a respective software asset of the set of software assets, and

corresponds to the set of memory accesses; and

collecting, using the set of memory accesses, the set of memory affinity data.

6. The method of claim 3 , further comprising:

configuring the set of identifiers to indicate a set of hardware chips related to the set of software assets, wherein a respective identifier indicates a respective hardware chip related to a respective software asset.

7. The method of claim 3 , further comprising:

configuring the set of identifiers to indicate a set of virtual machines, wherein a respective identifier indicates a respective virtual machine thereby tracking the set of events on a virtual-machine-by-virtual-machine basis.

8. The method of claim 3 , further comprising:

configuring the set of identifiers to indicate a set of containers, wherein a respective identifier indicates a respective container which utilizes an operating-system-level virtualization technique.

9. The method of claim 1 , further comprising:

monitoring, using a hardware unit which is coupled with a hardware processor component, the access relationship between the set of hardware memory components and the set of software assets; and

storing, in a special purpose register by the hardware unit, the set of memory affinity data which indicates the access relationship between the set of software assets and the set of hardware memory components.

10. The method of claim 9 , further comprising:

structuring the hardware unit to include a hardware processor performance monitoring unit (PMU);

configuring the hardware processor PMU to monitor a set of events corresponding to the access relationship between the set of software assets and the set of hardware memory components; and

collecting, based on the set of events, the set of memory affinity data.

11. The method of claim 1 , further comprising:

receiving a set of access requests from a set of hardware processors; and

capturing, pertaining to the set of memory affinity data and in response to receiving the set of access requests from the set of hardware processors, a set of identifiers of the set of hardware processors.

12. The method of claim 11 , further comprising:

carrying-out, by a hardware processor memory management unit (MMU) logic, a set of translations of a set of effective addresses to a set of real addresses; and

caching, in a set of effective-to-real address translation (ERAT) caches, the set of translations which pertain to the set of memory affinity data.

13. The method of claim 11 , further comprising:

receiving a new access request from an individual hardware processor of the set of hardware processors;

identifying, using a set of effective-to-real address translation (ERAT) caches, the individual hardware processor of the set of hardware processors; and

logging, pertaining to the set of memory affinity data, the new access request.

14. The method of claim 11 , further comprising:

receiving a new access request from an individual hardware processor of the set of hardware processors;

identifying, using a set of translation lookaside buffers (TLBs) of a set of page table entries (PTEs), the individual hardware processor of the set of hardware processors; and

logging, pertaining to the set of memory affinity data, the new access request.

15. The method of claim 1 , further comprising:

normalizing the set of memory affinity data to determine the NUMA utilization configuration with respect to the set of software assets;

weighting the set of memory affinity data to determine the NUMA utilization configuration with respect to the set of software assets; and

determining, based on and in response to both normalizing the set of memory affinity data and weighting the set of memory affinity data, the NUMA utilization configuration with respect to the set of software assets.

16. The method of claim 1 , further comprising

performing, in a dynamic fashion to streamline memory affinity management, each of

the monitoring,

the storing,

the determining, and

the executing.

17. The method of claim 1 , further comprising

performing, in an automated fashion without user intervention, each of

the monitoring,

the storing,

the determining, and

the executing.

18. A system for memory affinity management in a shared pool of configurable computing resources that utilizes non-uniform memory access (NUMA), the system comprising:

a memory having a set of computer readable computer instructions; and

a processor for executing the set of computer readable instructions, the set of computer readable instructions including

monitoring an access relationship between a set of hardware memory components and a set of software assets,

monitoring, using a hardware unit which is coupled with a hardware processor component, the access relationship between the set of hardware memory components and a set of containers which utilizes an operating-system-level virtualization technique,

structuring the hardware unit to include a hardware processor performance monitoring unit (PMU),

configuring the hardware processor PMU to monitor a set of events corresponding to the access relationship between the set of hardware memory components and the set of containers which utilizes the operating-system-level virtualization technique,

storing a set of memory affinity data which indicates the access relationship between the set of software assets and the set of hardware memory components,

determining, using the set of memory affinity data, a NUMA utilization configuration with respect to the set of software assets, and

executing, based on the NUMA utilization configuration, a set of accesses pertaining to the set of software assets and the set of hardware memory components;

storing, in a special purpose register by the hardware unit, the set of memory affinity data which indicates the access relationship between the set of hardware memory components and the set of containers which utilizes the operating-system-level virtualization technique,

tracking, using a set of identifiers related to the set of containers which utilizes the operating-system-level virtualization technique, the set of events corresponding to the access relationship between the set of hardware memory components and the set of containers which utilizes the operating-system-level virtualization technique,

configuring the set of identifiers to indicate both a set of hardware chips related to the set of containers and the set of containers, wherein a respective identifier indicates both a respective hardware chip related to a respective software asset and a respective container which utilizes the operating-system-level virtualization technique,

collecting, based on the set of events, the set of memory affinity data,

normalizing the set of memory affinity data to determine the NUMA utilization configuration with respect to the set of software assets,

weighting the set of memory affinity data to determine the NUMA utilization configuration with respect to the set of software assets,

determining, using the set of memory affinity data based on and in response to both normalizing the set of memory affinity data and weighting the set of memory affinity data, the NUMA utilization configuration with respect to the set of containers which utilizes the operating-system-level virtualization technique,

receiving a new access request from an individual hardware processor of a set of hardware processors,

identifying the individual hardware processor of the set of hardware processors,

executing, based on the NUMA utilization configuration, the new access request pertaining to the set of containers and the set of hardware memory components, and

logging, pertaining to the set of memory affinity data, the new access request.

19. A computer program product for memory affinity management in a shared pool of configurable computing resources that utilizes non-uniform memory access (NUMA), the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:

monitoring an access relationship between a set of hardware memory components and a set of software assets;

monitoring, using a hardware unit which is coupled with a hardware processor component, the access relationship between the set of hardware memory components and a set of containers which utilizes an operating-system-level virtualization technique;

structuring the hardware unit to include a hardware processor performance monitoring unit (PMU);

configuring the hardware processor PMU to monitor a set of events corresponding to the access relationship between the set of hardware memory components and the set of containers which utilizes the operating-system-level virtualization technique;

storing a set of memory affinity data which indicates the access relationship between the set of software assets and the set of hardware memory components;

determining, using the set of memory affinity data, a NUMA utilization configuration with respect to the set of software assets; and

executing, based on the NUMA utilization configuration, a set of accesses pertaining to the set of software assets and the set of hardware memory components;

storing, in a special purpose register by the hardware unit, the set of memory affinity data which indicates the access relationship between the set of hardware memory components and the set of containers which utilizes the operating-system-level virtualization technique;

tracking, using a set of identifiers related to the set of containers which utilizes the operating-system-level virtualization technique, the set of events corresponding to the access relationship between the set of hardware memory components and the set of containers which utilizes the operating-system-level virtualization technique;

configuring the set of identifiers to indicate both a set of hardware chips related to the set of containers and the set of containers, wherein a respective identifier indicates both a respective hardware chip related to a respective software asset and a respective container which utilizes the operating-system-level virtualization technique;

collecting, based on the set of events, the set of memory affinity data;

normalizing the set of memory affinity data to determine the NUMA utilization configuration with respect to the set of software assets;

weighting the set of memory affinity data to determine the NUMA utilization configuration with respect to the set of software assets;

determining, using the set of memory affinity data based on and in response to both normalizing the set of memory affinity data and weighting the set of memory affinity data, the NUMA utilization configuration with respect to the set of containers which utilizes the operating-system-level virtualization technique;

receiving a new access request from an individual hardware processor of a set of hardware processors;

identifying the individual hardware processor of the set of hardware processors;

executing, based on the NUMA utilization configuration, the new access request pertaining to the set of containers and the set of hardware memory components; and

logging, pertaining to the set of memory affinity data, the new access request.