Management of data transaction from I/O devices
Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.
1. A system for management of data transactions from I/O devices, comprising:
one or more processors; and
at least one memory, the memory including instructions that, upon execution by at least one of the one or more processors, wherein the one or more processors are configured to:
receive, via a link interface, a packet from an I/O device, wherein the packet includes address information;
perform an address translation for the address information included in the packet;
responsive to performing the address translation, determine a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page;
append a flag to a command based at least in part on the target page associated with the translated address of the packet; and
transmit the command to an ordering controller for processing the packet;
wherein the packet includes at least one of a signaling or a payload data;
responsive to the flag being set, the one or processors are configured to ignore an ordering of the payload data when writing the payload data into memory; and
responsive to the flag not being set, pushing out all preceding payload data, regardless of previously received payload data having the flag set.
2. The system of claim 1 , wherein the flag is set based on an ordering hint bit of an address translation table being set by a program.
3. The system of claim 2 , wherein the program is one of an operating system O/S, a driver, or an application.
4. The system of claim 1 , wherein the link interface is a peripheral component interconnect PCI-Express link interface, wherein the address information of the packet is a PCI-Express address, and wherein the ordering controller is a PCI-Express bridge controller.
5. The system of claim 4 , wherein the address translation converts the PCI-Express address of the packet to a memory location address of the memory.
6. A computer program product for management of data transactions from I/O, the computer program product comprising:
a computer readable storage medium having stored thereon first program instructions executable by a processor to cause the processor to:
receive a packet from an I/O device, wherein the packet includes address information;
perform an address translation for the address information included in the packet;
responsive to performing the address translation, determine a target page associated with a translated address of the packet is for at least one of a payload target page and a signaling target page;
append a flag to a command based at least in part on the target page associated with the translated address of the packet;
transmit the command to an ordering controller for processing the packet;
wherein the packet includes at least one of a signaling or a payload data;
responsive to the flag being set, ignore an ordering of the payload data when writing the payload data into memory; and
responsive to the flag not being set, pushing out all preceding payload data, regardless of previously received payload data having the flag set.
7. The computer program product of claim 6 , wherein the flag is set based on an ordering hint bit of an address translation table being set by a program.
8. The computer program product of claim 6 , wherein the packet is received at link interface, the link interface being a peripheral component interconnect PCI-Express link interface, wherein the address information of the packet is a PCI-Express address, and wherein the ordering controller is a PCI-Express bridge controller.