Integrated circuit die having backside passive components and methods associated therewith
Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, the IC die may include a semiconductor substrate, a plurality of active components disposed on a first side of the semiconductor substrate, and a plurality of passive components disposed on a second side of the semiconductor substrate. In embodiments the second side may be disposed opposite the first side. The passive components may, in some embodiments, include capacitors and/or resistors while the active components may, in some embodiments, include transistors. Other embodiments may be described and/or claimed.
1. An integrated circuit (IC) die comprising:
a semiconductor substrate;
a plurality of active components disposed on a first side of the semiconductor substrate;
two or more passive components, including two or more metal-insulator-metal (MIM) capacitors or trench capacitors, disposed on a second side of the semiconductor substrate, wherein the second side is disposed opposite the first side;
one or more first layers of electrically insulative material disposed on the first side of the semiconductor substrate, wherein the one or more first layers of electrically insulative material encapsulate the plurality of active components; and
one or more redistribution layers (RDLs) disposed on the second side of the semiconductor substrate, wherein the one or more redistribution layers include:
one or more second layers of electrically insulative material disposed on the second side of the semiconductor substrate, wherein the one or more second layers of electrically insulative material encapsulate the two or more passive components.
2. The IC die of claim 1 , further comprising a plurality of through-substrate vias (TSVs) disposed in the semiconductor substrate and configured to route electrical signals between one or more of the two or more passive components and the first side of the semiconductor substrate.
3. The IC die of claim 1 , further comprising:
a plurality of die-level interconnects disposed in the one or more first layers of the electrically insulative material; and
electrical routing features disposed in the one or more first layers of electrically insulative material, wherein the electrical routing features are configured to electrically couple the die-level interconnects with the plurality of active components.
4. The IC die of claim 1 , wherein the
one or more redistribution layers (RDLs) further include:
a plurality of input/output (I/O) interconnect structures disposed in the one or more second layers of the electrically insulative material; and
second electrical routing features disposed in the one or more second layers of electrically insulative material, wherein the second electrical routing features are configured to electrically couple the plurality of I/O interconnect structures with the two or more passive components.
5. The IC die of claim 1 , wherein the two or more passive components comprise two or more MIM capacitors, wherein each of the MIM capacitors includes a first metal layer, a capacitor dielectric layer disposed on the first metal layer, and a second metal layer disposed on the capacitor dielectric layer.
6. The IC die of claim 1 , wherein the two or more passive components comprise two or more trench capacitors, wherein each of the two or more trench capacitors include a first metal layer disposed on one or more trenches formed in the semiconductor substrate, a capacitor dielectric layer disposed on the first metal layer, and a second metal layer disposed on the capacitor dielectric layer.
7. The IC die of claim 5 , wherein the first and second metal layers are respectively electrically coupled with first and second interconnect structures disposed in one or more redistribution layers (RDLs) that are disposed on the second side of the semiconductor substrate.
8. The IC die of claim 6 , wherein the first metal layer is electrically coupled with a TSV disposed in the semiconductor substrate, wherein the TSV electrically couples the first side of the semiconductor substrate with the second side of the semiconductor substrate.
9. The IC die of claim 8 , wherein the second metal layer is electrically coupled with an electrical routing structure of the IC die, wherein the electrical routing structure is selected from a group consisting of:
an additional TSV disposed in the semiconductor substrate, wherein the additional TSV electrically couples the first side of the semiconductor substrate with the second side of the semiconductor substrate; or
an interconnect structure disposed in one or more redistribution layers (RDLs) that are disposed on the second side of the semiconductor substrate.
10. The IC die of claim 1 , wherein the two or more passive components further comprise at least one thin film resistor, wherein each thin film resistor includes a first terminal and a second terminal.
11. The IC die of claim 10 , wherein the first and second terminal are respectively electrically coupled with first and second interconnect structures disposed in one or more redistribution layers (RDLs) that are disposed on the second side of the semiconductor substrate.
12. The IC die of claim 10 , wherein the first terminal is electrically coupled with a TSV disposed in the semiconductor substrate, wherein the TSV electrically couples the first side of the semiconductor substrate with the second side of the semiconductor substrate.
13. The IC die of claim 12 , wherein the second terminal is electrically coupled with an electrical routing structure of the IC die, wherein the electrical routing structure is selected from a group consisting of:
an additional TSV disposed in the semiconductor substrate, wherein the additional TSV electrically couples the first side of the semiconductor substrate with the second side of the semiconductor substrate; or
an interconnect structure disposed in one or more redistribution layers (RDLs) that are disposed on the second side of the semiconductor substrate.
14. The IC die of claim 1 , wherein the plurality of active components comprise transistors.
15. The IC die of claim 1 , wherein the semiconductor substrate comprises a silicon wafer.
16. The IC die of claim 3 , wherein the one or more redistribution layers (RDLs) further include:
two or more of input/output (I/O) interconnect structures disposed in the one or more second layers of the electrically insulative material; and
second electrical routing features disposed in the one or more second layers of electrically insulative material, wherein the second electrical routing features are configured to electrically couple the two or more I/O interconnect structures with the two or more passive components.
17. An integrated circuit (IC) die comprising:
a semiconductor substrate;
a plurality of active components disposed on a first side of the semiconductor substrate;
two or more passive components, including two or more metal-insulator-metal (MIM) capacitors or trench capacitors, disposed on a second side of the semiconductor substrate, wherein the second side is disposed opposite the first side;
one or more first layers of electrically insulative material disposed on the first side of the semiconductor substrate, wherein the one or more first layers of electrically insulative material encapsulate the plurality of active components; and
one or more redistribution layers (RDLs) disposed on the second side of the semiconductor substrate, wherein the one or more redistribution layers include:
one or more second layers of electrically insulative material disposed on the second side of the semiconductor substrate, wherein the one or more second layers of electrically insulative material encapsulate the two or more passive components; and
a plurality of input/output (I/O) interconnect structures disposed in the one or more second layers of the electrically insulative material.
18. The IC die of claim 17 , wherein the one or more redistribution layers further include:
second electrical routing features disposed in the one or more second layers of electrically insulative material, wherein the second electrical routing features are configured to electrically couple the plurality of I/O interconnect structures with the two or more passive components.
19. The IC die of claim 17 , wherein the two or more passive components are selected from a group consisting of: capacitors or resistors.
20. The IC die of claim 17 , further comprising:
a plurality of die-level interconnects disposed in the one or more first layers of the electrically insulative material; and
electrical routing features disposed in the one or more first layers of electrically insulative material, wherein the electrical routing features are configured to electrically couple the die-level interconnects with the plurality of active components.