Precise junction placement in vertical semiconductor devices using etch stop layers
A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.
1. A method of fabricating a vertical fin field effect transistor (FinFET) comprising;
forming a first source/drain region of first composition epitaxial semiconductor material, wherein a semiconductor etch stop layer of a second epitaxial semiconductor material is present between two layers of the first composition epitaxial semiconductor material for the first source/drain region;
forming a material layer stack including at least a channel semiconductor material atop the first of the first source/drain region of the device; and
etching the material layer stack to provide a channel region selectively to the semiconductor etch stop layer.
2. The method of claim 1 , further comprising forming a gate structure on the channel region.
3. The method of claim 2 , wherein forming the first source/drain region comprises:
epitaxially growing a first portion of said first epitaxial semiconductor material that is in situ doped atop a strain relaxed buffer layer;
epitaxially growing the semiconductor etch stop layer on the first portion of the first epitaxial semiconductor material; and
epitaxially growing a second portion of said first epitaxial semiconductor material that is in situ doped atop the semiconductor etch stop layer.
4. The method of claim 3 , wherein the semiconductor etch stop layer comprises an indium and phosphorus containing material.
5. The method of claim 3 , wherein said etching the material layer stack to provide a channel region selectively to the semiconductor etch stop layer comprises:
etching the material stack selectively to the first portion of the first of the source/drain region; and
etching the first portion of the first source/drain region selectively to the semiconductor etch stop layer, wherein an etched first portion of the first source/drain region has a width equal to a width of the channel semiconductor material, wherein the etched first portion of the first source/drain region that has been etched provides an extension region for the first of the first source/drain region that overlaps with the channel region.
6. The method of claim 5 , wherein the material stack comprises a second source/drain region atop the channel semiconductor material.
7. The method of claim 6 , wherein forming the gate structure comprises:
forming a first spacer on the first source/drain region;
forming a gate dielectric layer on the channel region;
forming a gate conductor on the gate dielectric and overlying the first spacer; and
forming a second spacer on the gate conductor, wherein an overlap between the first source/drain region and the channel region of the device is a portion of the first source/drain region that extends past the interface surface of the first spacer with the recessed surface of the first source/drain region.
8. The method of claim 6 , wherein the first source/drain region and a second source/drain region have a same conductivity type.
9. A method of fabricating a vertical tunnel field effect transistor comprising;
forming a first source/drain region having a majority composition of a first epitaxial semiconductor material and a first conductivity type, wherein a semiconductor etch stop layer of a second epitaxial semiconductor material is present within said first source/drain region between two layers of the first composition epitaxial semiconductor material;
forming a material stack including at least a channel semiconductor material atop the first source/drain region of the device;
etching the material stack to provide a channel region selectively to the semiconductor etch stop layer; and
forming a second source/drain region having a second conductivity type positioned on the channel region.
10. The method of claim 9 , further comprising forming a gate structure on the channel region.
11. The method of claim 10 , wherein forming the first source/drain region comprises:
epitaxially growing a first portion of said first epitaxial semiconductor material that is in situ doped atop a strain relaxed buffer layer;
epitaxially growing the semiconductor etch stop layer on the first portion of the first epitaxial semiconductor material; and
epitaxially growing a second portion of said first epitaxial semiconductor material that is in situ doped atop the semiconductor etch stop layer.
12. The method of claim 11 , wherein the first epitaxial semiconductor material comprises a type III-V semiconductor material.
13. The method of claim 12 , wherein the semiconductor etch stop layer comprises an indium and phosphorus containing material.
14. The method of claim 11 , wherein said etching the material layer stack to provide a channel region selectively to the semiconductor etch stop layer comprises:
etching the material stack selectively to the first portion of the first source/drain region; and
etching the first portion of the first source/drain region selectively to the semiconductor etch stop layer, wherein an etched first portion of the first source/drain region has a width equal to a width of the channel semiconductor material, wherein the etched first portion of the first source/drain region that has been etched provides an extension region for the first source/drain region that overlaps with a channel region.
15. The method of claim 14 , wherein the second source/drain region is an epitaxial material.
16. A method of forming a semiconductor device comprising:
forming a first portion of a first source/drain region comprised of a first layer of first semiconductor material having a first conductivity type;
forming an etch stop layer of a second semiconductor material present on the first layer of the first semiconductor material having the first conductivity type;
forming a second layer of the first semiconductor material having the first conductivity type present on the etch stop layer to provide a second portion of the first source/drain region;
forming a channel semiconductor material is present atop the first source/drain region; and
forming a second source/drain region present atop the channel semiconductor material.
17. The method of claim 16 , wherein the etch stop layer comprises indium and phosphorus.
18. The method of claim 16 , wherein the first source/drain region and the second source/drain region are doped to a same conductivity type, wherein the semiconductor device is a vertically orientated fin field effect transistor.
19. The method of claim 16 , wherein the first source/drain region and the second source/drain region are doped to an opposite conductivity type, wherein the semiconductor device is a vertically orientated tunnel field effect transistor.
20. The method of claim 16 , further comprising forming a gate structure.