Digital phase controlled PLLs

1. A phase-locked loop (PLL) comprising:

an oscillator configured to generate a PLL output signal at an output of the PLL responsive to a reference signal input to the PLL;

a detector configured to compare the reference signal to a feedback signal to control a frequency of the PLL output signal, the feedback signal derived by a feedback path of the PLL from the PLL output signal; and

a phase control circuit operatively connected to the feedback path of the PLL, said phase control circuit configured to generate a timing control signal responsive to a phase control signal, wherein application of the timing control signal to the feedback path shifts a timing of one or more pulses of the feedback signal to achieve a desired average time shift to generate a desired phase shift at the output of the PLL while maintaining a desired average divisor of the feedback signal;

wherein the phase control circuit comprises:

a modulation circuit configured to generate a modulated output responsive to the phase control signal; and

a filter operatively connected to an output of the modulator and configured to filter the modulated output to generate the timing control signal; and

wherein the feedback path of the PLL comprises:

a combiner configured to combine the timing control signal with an input frequency divisor to generate a modified frequency divisor; and

a frequency divider configured to divide the frequency of the PLL output signal by the modified frequency divisor such that one or more pulses of the resulting feedback signal are time shifted while the desired average divisor of the feedback signal is maintained; and

wherein the filter comprises:

a delay element configured to delay the modulated output to generate a delayed modulated output; and

a second combiner configured to subtract the delayed modulated output from the modulated output to generate the timing control signal.

2. The PLL of claim 1 wherein the feedback path of the PLL comprises:

a frequency divider configured to divide the frequency of the PLL output signal by a frequency divisor;

a multiplexer controlled by the timing control signal, the multiplexer comprising a multiplexer output operatively connected to the detector and a plurality of multiplexer input connections; and

a delay line comprising a plurality of serially connected delay elements operatively connected between the frequency divider and the multiplexer, said plurality of multiplexer input connections comprising an output of the frequency divider and an output of at least some of the plurality of delay elements;

wherein the multiplexer is configured to periodically select, responsive to the timing control signal, the signal at one of the plurality of multiplexer inputs as the feedback signal.

3. The PLL of claim 2 wherein the phase control circuit comprises a modulation circuit configured to generate the timing control signal responsive to the phase control signal.

4. A method of controlling a phase at an output of a phase-locked loop (PLL) to achieve a desired phase shift at the output of the PLL, the method comprising:

generating a PLL output signal at the output of the PLL responsive to a reference signal input to the PLL;

comparing the reference signal to a feedback signal in a detector to control a frequency of the PLL output signal, the feedback signal derived by a feedback path of the PLL from the PLL output signal;

generating a timing control signal responsive to a phase control signal; and

shifting a timing, responsive to the timing control signal, of one or more pulses of the feedback signal to achieve a desired average time shift to generate a desired phase shift at the output of the PLL while maintaining a desired average divisor of the feedback signal;

wherein generating the timing control signal comprises:

generating a modulated output responsive to the phase control signal; and

filtering the modulated output to generate the timing control signal;

wherein shifting the timing of the one or more pulses of the feedback signal comprises:

combining the filtered modulated output with an input frequency divisor to generate a modified frequency divisor; and

dividing the frequency of the PLL output signal by the modified frequency divisor such that the one or more pulses of the feedback signal are time shifted while the desired average divisor of the feedback signal is maintained; and

wherein filtering the modulated output comprises:

delaying the modulated output by one reference signal period to generate a delayed modulated output; and

subtracting the delayed modulated output from the modulated output to generate the filtered modulated output.

5. The method of claim 4 further comprising:

dividing, in a frequency divider, the frequency of the PLL output signal by a frequency divisor; and

generating a plurality of multiplexer signal inputs by delaying an output of the frequency divider using a plurality of serially connected delay elements, said plurality of multiplexer signal inputs comprising the output of the frequency divider and an output of at least some of the plurality of delay elements;

wherein shifting the timing of the one or more pulses of the feedback signal comprises periodically selecting, responsive to the timing control signal, one of the plurality of multiplexer signal inputs as the feedback signal.

6. A computer program product stored in a non-transitory computer readable medium for controlling a phase at an output of a phase-locked loop (PLL) to achieve a desired phase shift at the output of the PLL, the computer program product comprising software instructions which, when run on a processing circuit, causes the processing circuit to:

generate a PLL output signal at the output of the PLL responsive to a reference signal input to the PLL;

compare the reference signal to a feedback signal in a detector to control a frequency of the PLL output signal, the feedback signal being derived by a feedback path of the PLL from the PLL output signal;

generate a timing control signal responsive to a phase control signal; and

shift a timing, responsive to the timing control signal, of one or more pulses of the feedback signal to achieve a desired average time shift to generate a desired phase shift at the output of the PLL while maintaining a desired average divisor of the feedback signal;

wherein the generation of the timing control signal comprises:

generating a modulated output responsive to the phase control signal; and

filtering the modulated output to generate the timing control signal;

wherein the shifting of the timing of the one or more pulses of the feedback signal comprises:

combining the filtered modulated output with an input frequency divisor to generate a modified frequency divisor; and

dividing the frequency of the PLL output signal by the modified frequency divisor such that the one or more pulses of the feedback signal are time shifted while the desired average divisor of the feedback signal is maintained; and

wherein the filtering of the modulated output comprises:

delaying the modulated output by one reference signal period to generate a delayed modulated output; and

subtracting the delayed modulated output from the modulated output to generate the filtered modulated output.