Semiconductor device and memory access control method

1. A semiconductor device comprising:

a memory unit comprising a lower-order memory to store data and a cache memory to cache the data stored in the lower-order memory;

a power control circuit to control power supply of the lower-order memory; and

a bus master coupled to the memory unit via a bus and to access the data stored in the memory unit after locking the bus,

wherein in response to a determination that the power supply of the lower-order memory is in an off state at the time of occurrence of a mishit of the cache memory, the power control circuit restores the power supply of the lower-order memory and the memory unit outputs to the bus master a response to an access by the bus master to the data stored in the memory unit, and

wherein the bus master releases lock of the bus according to the response from the memory unit and reexecutes the access with the bus locked, after the restoration of the power supply of the lower-order memory is completed.

2. The semiconductor device according to claim 1 ,

wherein in response to a determination that the access from the bus master is normal, the memory unit outputs, to the bus master, normal completion data indicating that the access has completed as a response to the access; and in response to a determination that the access from the bus master is not normal, the memory unit outputs, to the bus master, error completion data indicative of the error completion of the access as a response to the access,

wherein after the bus master receives the normal completion data from the memory unit or after the bus master receives the error completion data as the response from the memory unit, the bus master releases the lock of the bus, and

wherein in response to a determination that the mishit of the cache memory occurs and the power supply of the lower-order memory is in the off state, the memory unit outputs the error completion data to the bus master as a response.

3. The semiconductor device according to claim 2 ,

wherein in response to a determination that the error completion data is output from the memory unit, the bus master reexecutes the access,

wherein in response to a determination that the power supply of the lower-order memory is in the off state at the time of occurrence of the mishit of the cache memory, the memory unit outputs a cache miss interrupt signal, and

wherein in response to a determination that the cache miss interrupt signal is output from the memory unit and the error completion data is output from the memory unit, the bus master suppresses the reexecution of the access with the bus locked until the completion of restoration of the power supply of the lower-order memory.

4. The semiconductor device according to claim 3 ,

wherein the memory unit outputs the cache miss interrupt signal to the power control circuit,

wherein the power control circuit restores the power supply of the lower-order memory according to the cache miss interrupt signal from the memory unit and outputs the cache miss interrupt signal to the bus master, and

wherein the bus master recognizes the output of the cache miss interrupt signal from the memory unit by receiving the cache miss interrupt signal from the power control circuit.

5. The semiconductor device according to claim 3 ,

wherein the memory unit outputs the cache miss interrupt signal to the bus master,

wherein the bus master recognizes the output of the cache miss interrupt signal from the memory unit by receiving the cache miss interrupt signal from the memory unit and outputs, to the power control circuit, a signal indicative of the restoration of the power supply of the lower-order memory, according to the cache miss interrupt signal inputted from the memory unit, and

wherein the power control circuit restores the power supply of the lower-order memory according to the signal from the bus master.

6. The semiconductor device according to claim 1 ,

wherein the bus master is a DMA controller,

wherein the semiconductor device further comprises a CPU,

wherein in response to a determination that the power supply of the lower-order memory is in the off state at the time of occurrence of the mishit of the cache memory, the memory unit outputs a cache miss interrupt signal, and

wherein in response to a determination that a cache miss interrupt signal is outputted from the memory unit, the CPU deters the DMA controller from reexecuting the access with the bus locked until the completion of restoration of the power supply of the lower-order memory.

7. The semiconductor device according to claim 4 ,

wherein when the time set in advance as time until the completion of the restoration of the power supply of the lower-order memory since the input of the cache miss interrupt signal outputted from the power control circuit has elapsed, the bus master assumes that the restoration of the power supply of the lower-order memory has completed and reexecutes the access with the bus locked.

8. The semiconductor device according to claim 1 ,

wherein the semiconductor device further comprises a timer to measure a lapse of the time specified by the bus master and to output a timer interrupt signal to the bus master when the specified time concerned has elapsed,

wherein the bus master instructs the power control circuit to cutoff the power supply of the lower-order memory, according to the timer interrupt signal from the timer, and

wherein the power control circuit cuts off the power supply of the lower-order memory, according to the instruction from the bus master.

9. The semiconductor device according to claim 1 ,

wherein the lower-order memory is a main memory.

10. The semiconductor device according to claim 9 , wherein the main memory is a nonvolatile memory.

11. A memory access control method comprising the steps of:

making a bus master access data stored in a memory unit after locking a bus, the bus master being coupled, via the bus, to the memory unit comprising a lower-order memory to store data and a cache memory to cache data stored in the lower-order memory;

in response to a determination that power supply of the lower-order memory is in an off state at the time of occurrence of a mishit of the cache memory, restoring the power supply of the lower-order memory;

making the memory unit transmit to the bus master a response to an access by the bus master to the data stored in the memory unit; and

making the bus master release the lock of the bus according to the response from the memory unit and reexecute the access with the bus locked, after the restoration of the power supply of the lower-order memory is completed.