SRAM bitline equalization using phase change material
Embodiments include techniques for static random access memory (SRAM) bitline equalization using phase change material (PCM). The techniques include detecting a defect in SRAM bitlines, and programming a variable resistance PCM cell to offset the detected defect. The techniques also include measuring signal development time for the SRAM bitlines, and adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development for the SRAM bitlines.
1. A system for static random access memory (SRAM) bitline equalization using phase change material (PCM), the system comprising: an SRAM including bitlines and a plurality of transistors; a pre-charge circuit coupled to the bitlines of the SRAM for pre-charging the bitlines to a high state; a sense amplifier, coupled to the bitlines, for periodically sampling the bitlines and outputting data based at least in part on a signal differential of the bitlines; and a variable resistance PCM cell, coupled to at least one of the bitlines, configured, based at least in part on a defect being detected by the sense amplifier, to offset the detected defect of the signal differential of the bitlines.
2. The system of claim 1 , wherein the variable resistance PCM cell is coupled to a first or second bitline of the bitlines of the SRAM based at least in part on the detected defect.
3. The system of claim 1 , wherein a first variable resistance PCM cell is coupled to a first bitline of the bitlines and a second variable resistance PCM cell is coupled to a second bitline of the bitlines.
4. The system of claim 1 , wherein bitline isolation transistors are coupled to a first bitline of the bitlines and a second bitline of the bitlines.
5. The system of claim 1 , comprising a voltage source for programming the variable resistance PCM cell.
6. The system of claim 1 , wherein the variable resistance PCM cell is coupled to the pre-charge circuit providing a current path for the variable resistance PCM cell for offsetting the detected defect.
7. The system of claim 1 , wherein the variable resistance PCM cell is coupled to a dedicated transistor providing a current path for the variable resistance PCM cell for offsetting the detected defect.