Semiconductor memory devices including protrusion pads
Disclosed is a semiconductor memory device may include a substrate including a cell array region and a contact region and a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on the substrate. The stacking structure may include a stepwise structure in the contact region. Ones of the plurality of gate electrodes may include a respective pad unit that comprises a step of the stepwise structure. At least one of the pad units may include a base pad and a protrusion pad on the base pad. The protrusion pad may be between and spaced apart from two edges of a surface of the base pad that are perpendicular to an extension direction of the respective gate electrode.
1. A semiconductor memory device comprising:
a substrate comprising a cell array region and a contact region;
a stacking structure comprising a plurality of insulating layers and a plurality of gate electrodes alternately stacked on the substrate, the stacking structure comprising a stepwise structure in the contact region, wherein ones of the plurality of gate electrodes comprise a respective pad unit that comprises a step of the stepwise structure; and
contact plugs on the pad units,
wherein at least one of the pad units comprises a base pad and a protrusion pad on the base pad,
wherein the protrusion pad is between and spaced apart from two edges of a surface of the base pad that are perpendicular to an extension direction of the respective gate electrode,
wherein the protrusion pad contacts one of the contact plugs,
wherein the protrusion pad extends from a portion of the base pad, and
wherein an area of the protrusion pad is smaller than an area of the base pad in a plan view.
2. The semiconductor memory device of claim 1 , wherein the protrusion pad comprises an island shape that is on the base pad.
3. The semiconductor memory device of claim 1 , wherein a minimum distance between two adjacent pad units, among the pad units, is smaller than a thickness of an insulating layer positioned between the two adjacent pad units.
4. The semiconductor memory device of claim 1 , wherein the protrusion pad is between and spaced apart from two edges of the surface of the base pad that are parallel to the extension direction of the gate electrode.
5. The semiconductor memory device of claim 4 , wherein, in the stepwise structure, the pad units are inclined stepwise in the extension direction of the gate electrode and inclined stepwise in a direction that is perpendicular to the extension direction of the gate electrode.
6. The semiconductor memory device of claim 1 ,
wherein the at least one of the pad units that comprises a protrusion pad comprises a first pad unit adjacent to an uppermost insulating layer and a second pad unit adjacent to the substrate, and
wherein a width of the protrusion pad of the first pad unit adjacent to the uppermost insulating layer is larger than a width of the protrusion pad of the second pad unit adjacent to the substrate.
7. The semiconductor memory device of claim 1 , further comprising an auxiliary insulating layer on the pad units in the contact region.
8. The semiconductor memory device of claim 7 , wherein the auxiliary insulating layer contacts the surface of the base pad and side surface of the pad units.
9. The semiconductor memory device of claim 7 , wherein an uppermost surface of the auxiliary insulating layer and the uppermost surface of the protrusion pad are coplanar with each other.
10. A semiconductor memory device comprising:
a substrate comprising a cell array region and a contact region;
a stacking structure comprising a plurality of insulating layers and a plurality of gate electrodes alternately stacked on the substrate, the stacking structure comprising a stepwise structure in the contact region, wherein ones of the plurality of gate electrodes comprise a respective pad unit that comprises a step of the stepwise structure; and
contact plugs on the pad units,
wherein at least one of the pad units comprises a base pad and a protrusion pad on the base pad,
wherein the protrusion pad is between and spaced apart from two edges of a surface of the base pad that are perpendicular to an extension direction of the respective gate electrode,
wherein the protrusion pad contacts one of the contact plugs, and
wherein a side of the protrusion pad is coplanar with a side of the base pad in a direction parallel to the extension direction of the gate electrode.
11. A semiconductor memory device comprising:
a substrate comprising a cell array region and a contact region;
a stacking structure comprising a plurality of insulating layers and a plurality of gate electrodes alternately stacked on the substrate, the stacking structure comprising a stepwise structure in the contact region, wherein ones of the plurality of gate electrodes comprise a respective pad unit that comprises a step of the stepwise structure; and
contact plugs on the pad units,
wherein at least one of the pad units comprises a base pad and a protrusion pad on the base pad,
wherein the protrusion pad is between and spaced apart from two edges of a surface of the base pad that are perpendicular to an extension direction of the respective gate electrode,
wherein the protrusion pad contacts one of the contact plugs, and
wherein the pad units' comprise at least one pad unit that does not include the protrusion pad.
12. The semiconductor memory device of claim 11 , wherein the at least one pad unit that does not include the protrusion pad comprises at least one pad unit adjacent to the substrate among the pad units that do not include the protrusion pad and at least one pad unit adjacent to an uppermost insulating layer among the pad units that do not include the protrusion pad.