IP Library Granted Patent US 10,229,932
Granted Patent B2
US 10,229,932 · App. 15/714,221 · Granted Mar 12, 2019

Voltage distribution in transistor stacks using non-uniform transistor dimensions

Inventor: David Scott Whitefield (Andover, MA)
Assignee: Skyworks Solutions, Inc.
H01L27/1203H01L27/0207H01L27/088H01L29/41725H01L29/41733
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Quick Facts
Patent No.
US 10,229,932
App. No.
15/714,221
Granted
Mar 12, 2019
Kind
B2
Abstract

A radio-frequency switch includes a first field-effect transistor having drain and source fingers separated by a first drain-to-source distance and a second field-effect transistor in a series connection with the first field-effect transistor, the second field-effect transistor having drain and source fingers separated by a second drain-to-source distance that is different than the first drain-to-source distance.

Claims (25)

1. A radio-frequency switch comprising:

a first transistor having a first source finger, a first drain finger, and a first gate finger, the first gate finger having a first gate width, the first source finger and the first drain finger being separated by a first drain-to-source distance;

a second transistor connected in series with the first transistor, the second transistor having a second source finger, a second drain finger, and a second gate finger, the second gate finger having a second gate width that is greater than the first gate width, the second source finger and the second drain finger being separated by a second drain-to-source distance that is greater than the first drain-to-source distance; and

a third transistor connected in series with the second transistor, the third transistor having a third source finger, a third drain finger, and a third gate finger, the third gate finger having a third gate width that is greater than the second gate width, the third source finger and the third drain finger being separated by a third drain-to-source distance that is greater than the second drain-to-source distance.

2. The radio-frequency switch of claim 1 wherein the first transistor is coupled to an antenna node of an antenna switch circuit.

3. The radio-frequency switch of claim 1 wherein the third transistor is coupled to a throw node of an antenna switch circuit.

4. The radio-frequency switch of claim 1 wherein the first, second, and third transistors are silicon-on-insulator transistors.

5. The radio-frequency switch of claim 1 wherein the first transistor occupies a smaller physical area than the second transistor.

6. A radio-frequency module comprising:

a first field-effect transistor having a first plurality of source fingers, a first plurality of drain fingers, and a first plurality of gate fingers, each of the first plurality of source fingers being separated from an adjacent drain finger of the first plurality of drain fingers by a first drain-to-source distance;

a second field-effect transistor connected in series with, and adjacent to, the first field-effect transistor, the second field-effect transistor having a second plurality of source fingers, a second plurality of drain fingers, and a second plurality of gate fingers, each of the second plurality of source fingers being separated from an adjacent drain finger of the second plurality of drain fingers by a second drain-to-source distance that is greater than the first drain-to-source distance; and

a third field-effect transistor connected in series with, and adjacent to, the second field-effect transistor, the third field-effect transistor having a third plurality of source fingers, a third plurality of drain fingers, and a third plurality of gate fingers, each of the third plurality of source fingers being separated from an adjacent drain finger of the third plurality of drain fingers by a third drain-to-source distance that is greater than the second drain-to-source distance.

7. The radio-frequency module of claim 6 wherein the first field-effect transistor is coupled to an antenna node of an antenna switch circuit.

8. The radio-frequency module of claim 6 wherein the third field-effect transistor is coupled to a throw node of an antenna switch circuit.

9. The radio-frequency module of claim 6 further comprising a fourth field-effect transistor connected in series with the third field-effect transistor, the fourth field-effect transistor having a fourth plurality of source fingers, a fourth plurality of drain fingers, and a fourth plurality of gate fingers, each of the fourth plurality of source fingers being separated from an adjacent drain finger of the fourth plurality of drain fingers by a fourth drain-to-source distance that is equal to the third drain-to-source distance.

10. The radio-frequency module of claim 6 wherein the first plurality of gate fingers comprises more gate fingers than the second plurality of gate fingers.

11. The radio-frequency module of claim 6 wherein the first plurality of gate fingers has a first gate width that is shorter than a second gate width of the second plurality of gate fingers.

12. The radio-frequency module of claim 6 wherein the first field-effect transistor has a total periphery that is greater than a total periphery of the second field-effect transistor.

13. The radio-frequency module of claim 6 wherein at least some of the first plurality of drain fingers have metal traces electrically coupled thereto to provide added capacitance.

14. The radio-frequency module of claim 6 wherein the first field-effect transistor occupies a smaller physical area than the second field-effect transistor.

15. The radio-frequency module of claim 6 wherein the first field-effect transistor has a physical area equal to a physical area of the second field-effect transistor.

16. A method of fabricating a transistor stack comprising:

forming a first field-effect transistor on a semiconductor substrate, the first field-effect transistor having a first gate width and a first drain-to-source spacing;

forming a second field-effect transistor on the semiconductor substrate in a series connection with the first field-effect transistor, the second field-effect transistor having a second gate width that is greater than the first gate width and a second drain-to-source spacing that is greater than the first drain-to-source spacing; and

forming a third field-effect transistor on the semiconductor substrate in a series connection with the second field-effect transistor, the third field-effect transistor having a third gate width that is greater than the second gate width and a third drain-to-source spacing that is greater than the second drain-to-source spacing.

Continuity (3)
Continuation 15240771 · Aug 18, 2016
Provisional Application 62208540 · Aug 21, 2015
Related Publication 20180019261A1 · Jan 18, 2018