System and method for protecting an integrated circuit (IC) device

1. A method for protecting an integrated circuit (IC) device from attacks, the IC device comprising a substrate having a front surface and a back surface, the IC device further comprising a front side part arranged above the front surface of the substrate and comprising stacked layers, at least one of said layers comprising a data layer comprising wire carrying data, the front side part having a front surface, an internal shield being arranged in the IC device, below said data layer, wherein the method comprises computing a target value to be sent through a routing portion of the internal shield and checking if a condition is satisfied between a value received from said routing portion and said target value.

2. A system for protecting an integrated circuit (IC) device from attacks, the IC device comprising a substrate having a front surface and a back the IC device further comprising a front side part arranged above the front surface of the substrate and comprising stacked layers, at least one of said layers comprising a data layer comprising wire carrying data, the front side part having a front surface, wherein the system comprises an internal shield arranged in the IC device, below said data layer, said internal shield comprising a mesh of lines arranged according to a routing pattern, said internal shield being configured to propagate data, and a verification circuit configured to check integrity of a routing portion of the internal shield, said verification circuit being configured to propagate an input value inside said routing portion of internal shield and check the integrity of said input value at the output of said routing portion of the internal shield.

3. The system of claim 2 , wherein the internal shield comprises a mesh of lines, said mesh, being arranged in the empty areas of the layer in which the internal shield is arranged.

4. The system of claim 2 , wherein the substrate comprises doped areas and the internal shield is implemented in at least some of the doped areas.

5. The system of claim 2 , wherein the front-side part comprises standard cells, and the internal shield is implemented in areas between standard cells.

6. The system of claim 2 , wherein the substrate comprises wells in doped regions and the internal shield is implemented in at least some of said wells.

7. The system of claim 2 , wherein the internal shield is arranged in the layer located on top of the substrate.

8. The system of claim 2 , wherein the internal shield is implemented in standard cells.

9. The system of claim 2 , wherein said integrated circuit device comprises security-critical transistors and a set of auxiliary transistors, each auxiliary transistor being coupled to one or more security-critical transistor, each auxiliary transistor being a backup transistor configured to perform the operations of a security-critical transistor coupled to said auxiliary transistor when said security-critical transistor is removed in an attack.

10. The system of claim 9 , wherein at least some of the auxiliary transistors are used to route portions of the internal shield.

11. The system of claim 2 , wherein the verification circuit comprises a computation unit for computing a target value to be sent through the routing portion of the internal shield and a comparison unit to check if a condition is satisfied between a value received at the output of said routing portion and said target value.

12. The system of claim 11 , wherein said computation unit is configured to implement a protection operation to compute said target value.