IP Library › Granted Patent US 10,236,311
Granted Patent B2
US 10,236,311 · App. 15/518,483 · Granted Mar 19, 2019

Solid-state imaging element and electronic device to improve quality of an image

Inventors: Ryoji Suzuki (Kanagawa, JP); Hitoshi Moriya (Tokyo, JP); Atsuhiro Ando (Kanagawa, JP); Atsushi Masagaki (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
H01L27/14609H01L27/146H01L27/1462H01L27/1464H01L27/14621H01L27/14623H01L27/14643H01L27/14645H01L27/14659H01L27/14667H01L31/022441H01L31/102H04N5/23212H04N5/369H04N5/374H04N5/378H04N9/045H01L27/14627H01L27/14634H01L27/14636H01L27/14812
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Quick Facts
Patent No.
US 10,236,311
App. No.
15/518,483
Granted
Mar 19, 2019
Kind
B2
Abstract

The present technology relates to a solid-state imaging element and an electronic device capable of improving image quality of the solid-state imaging element. The solid-state imaging element includes a photoelectric conversion unit adapted to photoelectrically convert incident light incident from a predetermined incident surface. Also, the solid-state imaging element includes a wire arranged on a bottom surface side that is an opposite surface of the incident surface of the photoelectric conversion unit, and formed with a protruding pattern on a surface facing the photoelectric conversion unit. The present technology can be applied to, for example, a solid-state imaging element such as a CMOS image sensor, and an electronic device including the solid-state imaging element.

Claims (20)

1. A solid-state imaging element, comprising:

a wiring layer, and

a photoelectric conversion unit configured to photoelectrically convert incident light incident from incident surface of the photoelectric conversion unit, wherein the photoelectric conversion unit includes a plurality of patterns, wherein positions of the plurality of patterns with respect to the wiring layer are misaligned from each other along a straight line in an extending direction of the wiring layer,

wherein the wiring layer is on a bottom surface side of the photoelectric conversion unit, wherein the bottom surface side is opposite to the incident surface, and wherein the wiring layer includes a protruding pattern on a surface that faces the photoelectric conversion unit.

2. The solid-state imaging element according to claim 1 , wherein the plurality of patterns are at different intervals in the extending direction of the wiring layer.

3. The solid-state imaging element according to claim 1 , wherein a pixel in a proximity to an outer periphery of the solid-state imaging element has a lower density of patterns in a direction vertical to a side of the outer periphery.

4. The solid-state imaging element according to claim 1 , wherein each of the positions of the plurality of patterns is different than a position of a first wire of the wiring layer, wherein the position of the first wire is closer to the photoelectric conversion unit than a position of a second wire, and wherein the second wire includes a set of patterns of the plurality of patterns.

5. The solid-state imaging element according to claim 1 , wherein a width of each of the plurality of patterns is based on a width of the wiring layer.

6. The solid-state imaging element according to claim 1 , wherein a pixel in proximity to a side of an outer periphery of the solid-state imaging element includes a set of patterns of the plurality of patterns, and wherein a length corresponding to the set of patterns in the extending direction of the wiring layer is greater than a threshold length.

7. The solid-state imaging element according to claim 1 ,

wherein the wiring layer comprises a plurality of wires,

wherein the plurality of patterns are not formed in a specific wire of the plurality of wires of the wiring layer, and

wherein the specific wire is closest to a bottom surface of the photoelectric conversion unit among the plurality of wires.

8. The solid-state imaging element according to claim 1 , wherein the plurality of patterns are in the photoelectric conversion unit of a pixel that receives light of a specific wavelength or more.

9. The solid-state imaging element according to claim 1 , wherein an arrangement of the plurality of patterns is based on at least one of a connection of wires of adjacent wiring layers or a connection of a wire of the wiring layer to a semiconductor substrate of the photoelectric conversion unit.

10. An electronic device, comprising:

a solid-state imaging element that comprises:

a wiring layer; and

a photoelectric conversion unit configured to photoelectrically convert incident light incident from incident surface of the photoelectric conversion unit, wherein the photoelectric conversion unit includes a plurality of patterns, and wherein positions of the plurality of patterns with respect to the wiring layer are misaligned from each other along a straight line in an extending direction of the wiring layer,

wherein the wiring layer is on a bottom surface side of the photoelectric conversion unit, wherein the bottom surface side is opposite to the incident surface, and wherein the wiring layer includes a protruding pattern on a surface that faces the photoelectric conversion unit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2017
From: SUZUKI, RYOJI; MORIYA, HITOSHI; ANDO, ATSUHIRO; MASAGAKI, ATSUSHI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 041972/0028 →
Priority Claims (1)
JP 2014-213767 · Oct 20, 2014 · national
Continuity (1)
Related Publication 20170229503A1 · Aug 10, 2017