Memory device for controlling refresh operation by using cell characteristic flags

1. A memory device comprising:

a memory cell array that includes a plurality of memory cell rows; and

a refresh address generator configured to

store, in a plurality of storage cells, flags respectively corresponding to the plurality of memory cell rows,

generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation,

read a first flag stored in a first storage cell from among the plurality of storage cells, in response to the generating the refresh row address of the memory cell row to which the first flag corresponds, and

according to the flags, change a refresh period of the plurality of memory cell rows.

2. The memory device of claim 1 , wherein the plurality of memory cell rows include one or more normal cell rows and one or more weak cell rows, and the refresh address generator is configured to determine each of the plurality of memory cell rows to be one of the one or more normal cell rows or one of the one or more weak cell rows according to at least one bit of the flags.

3. The memory device of claim 2 , wherein the refresh address generator is configured to

refresh the one or more normal cell rows according to the refresh period, and

refresh the one or more weak cell rows according to a shorter period than the refresh period.

4. The memory device of claim 1 , wherein the refresh address generator is configured to determine each of the plurality of memory cell rows to be a normal cell row or a strong cell row according to at least one bit of the flags.

5. The memory device of claim 4 , wherein the refresh address generator is configured to

refresh the normal cell row according to the refresh period, and

refresh the strong cell row according to a longer period than the refresh period.

6. The memory device of claim 1 , wherein the refresh address generator is configured to determine each of the plurality of memory cell rows to be a normal cell row, a weak cell row, or a strong cell row according to at least two bits of the flags.

7. The memory device of claim 6 , wherein the refresh address generator is configured to

refresh the normal cell row according to the refresh period,

refresh the weak cell row according to a period shorter than the refresh period, and

refresh the strong cell row according to a period longer period than the refresh period.

8. The memory device of claim 1 , wherein the refresh address generator comprises:

a counter configured to generate normal cell row addresses respectively corresponding to the memory cell rows by performing the count operation;

a storage that includes the storage cells that store the flags respectively corresponding to the plurality of memory cell rows, the storage being configured to output the flags;

a decoder configured to address the storage cells based on the refresh row addresses;

a latch configured to store the normal cell row addresses corresponding to the flags output from the storage as weak cell row addresses or strong cell row addresses; and

a selector configured to output the weak cell row addresses, the strong cell row addresses, or the normal cell row addresses as the refresh row addresses, according to the changed refresh period,

the normal cell row addresses being row addresses other than the weak and strong cell row addresses.

9. The memory device of claim 8 , wherein each of the storage cells stores the flags as 1-bit information.

10. The memory device of claim 8 , wherein each of the storage cells stores the flags as 2-bit information.

11. The memory device of claim 8 , wherein the storage cells are configured such that each of the storage cells stores the flags before the memory device is packaged.

12. The memory device of claim 8 , wherein the storage cells are configured such that each of the storage cells stores the flags after the memory device is packaged.

13. The memory device of claim 8 , wherein the storage cells are non-volatile memory and include at least one of

electric programmable fuse memory,

laser-programmable fuse memory,

anti-fuse memory,

one-time programmable memory, or

flash memory.

14. The memory device of claim 8 , wherein the refresh address generator further comprises:

a sense amplifier configured to sense-amplifies the flags output from the storage.

15. A refresh method of a memory device, the method comprising:

performing a count operation to generate refresh row addresses respectively corresponding to a plurality of memory cell rows;

storing, in a plurality of storage cells, flags that respectively correspond to the refresh row addresses and indicate weak cell rows that comprise at least one memory cell having a data retention time that is shorter than a refresh period;

reading a first flag stored in a first storage cell from among the plurality of storage cells, in response to the count operation generating the refresh row address to which the first flag corresponds;

refreshing the weak cell rows according to a shorter period than the refresh period; and

refreshing normal cell rows, which are memory cell rows other than the weak cell rows, according to the refresh period.

16. The method of claim 15 , wherein the performing of the count operation comprises:

initializing the refresh row addresses;

gradually increasing the refresh row addresses;

monitoring the flags that respectively correspond to the refresh row addresses; and

re-initializing the refresh row addresses when the increased refresh row addresses are greater than a maximum row address.

17. The method of claim 15 , wherein the storing of the flags comprises storing 1-bit flags in storage cells that respectively correspond to the refresh row addresses.

18. The method of claim 17 , wherein the storage cells are non-volatile memory, that is, one selected from electric programmable fuse memory, laser-programmable fuse memory, anti-fuse memory, one-time programmable memory, and flash memory.

19. A memory device comprising:

a memory cell array that includes a plurality of memory cell rows, respectively; and

a refresh address generator configured to

perform a count operation to generate a plurality of row addresses respectively corresponding to the plurality of memory cell rows,

store, in a plurality of storage cells, a plurality of flags, the plurality of flags corresponding to the plurality of row addresses, respectively,

determine a type, from among a plurality of types, of a first row address, from among the plurality of row addresses, the plurality of types including at least a first type and a second type,

refresh a first memory cell row at a first rate, when the determined type is the first type, the first memory cell row being the memory cell row, from among the plurality of memory cell rows, that corresponds to the first row address, and

refresh the first memory cell row at a second rate higher than the first rate, when the determined type is the second type,

the refresh address generator being further configured such that the determining of the type of the first row address includes,

reading a first flag stored in a first storage cell from among the plurality of storage cells, in response to the count operation generating the first row address, the first row address being the row address, from among the plurality of row addresses, to which the first flag corresponds.

20. The memory device of claim 19 , wherein the refresh address generator is configured to,

determine the type of the first row address to be the first type when the first flag indicates the first type, and

determine the type of the first row address to be the second type when the first flag indicates the second type.