Integrated circuit package substrate
Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.
1. An integrated circuit (IC) die comprising:
a semiconductor substrate;
an electrically insulative material disposed on the semiconductor substrate;
a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material;
a plurality of metal features coupled with the plurality of electrical routing features, wherein the plurality of metal features have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations; and
a transistor layer disposed between the substrate and the electrically insulative material, the transistor layer forming one or more hard intellectual property (HIP) input/output (I/O) blocks, wherein the plurality of electrical routing features are HIP routing features to route electrical signals from the plurality of metal features through the electrically insulative material to the one or more HIP I/O blocks.
2. The IC die of claim 1 , wherein the one or more HIP I/O blocks comprise respective logic circuits.
3. The IC die of claim 1 , wherein the one or more HIP I/O blocks are designed to align with the I/O density.
4. The IC die of claim 1 , wherein the I/O density is based, at least in part, on one or more boundary conditions respectively associated with each package configuration of the plurality of different package configurations.
5. The IC die of claim 1 , further comprising a plurality of interconnect structures disposed on the die, the plurality of interconnect structures coupled with the plurality of metal features, wherein the interconnect structures are to electrically couple the die with a selected one of the plurality of different package configurations.
6. The IC die of claim 5 , wherein the plurality of interconnect structures are coupled with one or more redistribution layers (RDLs) that electrically couple the plurality of interconnect structures with the plurality of metal features.
7. The IC die of claim 5 , wherein the plurality of interconnect structures comprise one or more of pillars, bumps, or solder balls.
8. The IC die of claim 1 , wherein the plurality of different package configurations includes one or more direct chip attach (DCA) circuit board configurations.
9. The IC die of claim 1 , wherein each individual package configuration, of the plurality of different package configurations, has an associated I/O density of the individual package configuration, and wherein the associated I/O densities of the individual packages vary.
10. A method of assembling an integrated circuit (IC) die comprising:
providing a semiconductor substrate;
depositing an electrically insulative material on the semiconductor substrate;
forming a plurality electrical routing features in the electrically insulative material to route electrical signals through the electrically insulative material;
forming a plurality of metal features coupled with the plurality of electrical routing features, wherein the plurality of metal features have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations; and
forming one or more hard intellectual property (HIP) I/O blocks by forming a layer of transistors on the semiconductor substrate prior to depositing the electrically insulative materials, wherein the plurality of electrical routing features route electrical signals from the plurality of metal features through the electrically insulative material to the one or more HIP I/O blocks.
11. The method of claim 10 , further comprising designing the one or more HIP I/O blocks to align with the I/O density.
12. The method of claim 10 , further comprising calculating one or more boundary conditions respectively associated with each package configuration of the plurality of different package configurations, wherein design of the I/O density is based, at least in part, on the one or more boundary conditions respectively associated with each package configuration of the plurality of different package configurations.
13. The method of claim 12 , wherein calculating the one or more boundary conditions respectively associated with each package configuration is based on one or more design rules associated with each package configuration of the plurality of different package configurations.
14. The method of claim 13 , wherein the design rules include at least one or more of a bump pitch, line spacing, or layer count.
15. The method of claim 10 , further comprising depositing a plurality of interconnect structures on a surface of the die, the plurality of interconnect structures being coupled with the plurality of metal features, wherein the interconnect structures electrically couple the die with a selected one of the plurality of different package configurations.
16. The method of claim 15 , wherein depositing the plurality of interconnect structures further comprises depositing one or more redistribution layers (RDLs), the one or more RDLs being electrically coupled with the plurality of interconnect structures.
17. The method of claim 10 , wherein the plurality of different package configurations includes one or more direct chip attach (DCA) circuit board configurations.