Semiconductor memory device

1. A semiconductor memory device, comprising:

a substrate;

an insulating layer provided on the substrate;

a conductive layer provided above the insulating layer;

a first pillar column having a plurality of semiconductor pillars, each of the plurality of semiconductor pillars extending in a vertical direction perpendicular to a surface of the conductive layer, the plurality of semiconductor pillars of the first pillar column being arranged by one sequence in a first direction intersecting with the vertical direction;

a second pillar column having a plurality of semiconductor pillars, each of the plurality of semiconductor pillars extending in the vertical direction, the plurality of semiconductor pillars of the second pillar column being arranged by one sequence in the first direction, the second pillar column being located in a second direction of the first pillar column, the second direction intersecting with the vertical direction and the first direction;

a first control column having a plurality of first electrode films extending in the first direction, the plurality of first electrode films of the first control column being disposed to be separated from each other along the vertical direction;

a second control column having a plurality of first electrode films extending in the first direction, the plurality of first electrode films of the second control column being disposed to be separated from each other along the vertical direction;

a third control column having a plurality of first electrode films extending in the first direction, the plurality of first electrode films of the third control column being disposed to be separated from each other along the vertical direction; and

a fourth control column having a plurality of first electrode films extending in the first direction, the plurality of first electrode films of the fourth control column being disposed to be separated from each other along the vertical direction;

wherein the first pillar column, the second pillar column, the first control column, the second control column, the third control column and the fourth control column being arranged in the second direction, the first pillar column being located between the first control column and the second control column, the second pillar column being located between the third control column and the fourth control column, the second control column and the third control column being located between the first pillar column and the second pillar column,

further wherein the first control column, the second control column, the third control column and the fourth control column are provided above the surface of the conductive layer, and lower ends of the semiconductor pillars of at least one of the first pillar column and the second pillar column are in contact with a recessed portion formed on the surface of the conductive layer.

2. The device according to claim 1 , further comprising:

a plurality of second electrode films provided between the semiconductor pillars and the first electrode films, the plurality of second electrode films being disposed to be separated from each other along the vertical direction, the first direction and the second direction;

a first insulating film provided between one of the semiconductor pillars and one of the second electrode films; and

a second insulating film provided between one of the second electrode films and one of the first electrode films.

3. The device according to claim 2 , wherein

an equivalent oxide thickness of the first insulating film is thicker than an equivalent oxide thickness of the second insulating film, and

a dielectric constant of the first insulating film is lower than a dielectric constant of the second insulating film.

4. The device according to claim 3 , wherein the second insulating film includes:

a first layer provided on the first electrode film side to cover an upper surface and a lower surface of the first electrode film; and

a second layer provided on the second electrode film side to cover an upper surface and a lower surface of the second electrode film.

5. The device according to claim 2 , wherein

an equivalent oxide thickness of the second insulating film is thicker than an equivalent oxide thickness of the first insulating film, and

a dielectric constant of the second insulating film is lower than a dielectric constant of the first insulating film.

6. The device according to claim 5 , wherein the first insulating film is disposed along a side surface of the semiconductor pillar.

7. The device according to claim 2 , wherein a length in the first direction of an end portion of the second electrode film on the semiconductor pillar side is shorter than a length in the first direction of an end portion of the second electrode film on the first electrode film side.

8. The device according to claim 2 , wherein the second insulating film is not disposed between the first electrode film and the second electrode film for the uppermost level or for a plurality of levels including the uppermost level, and the first electrode film is connected to the second electrode film for the uppermost level or for the plurality of levels including the uppermost level.

9. The device according to claim 2 , wherein the second insulating film is divided along the vertical direction for each of the first electrode films.

10. The device according to claim 1 , further comprising an interconnect layer provided between the insulating layer and the conductive layer.

11. The device according to claim 1 , wherein

the first pillar column, the second pillar column, the first control column, the second control column, the third control column and the fourth control column are located in a memory cell region, and

a transistor is formed under the conductive layer in a peripheral circuit region.