IP Library Granted Patent US 10,243,056
Granted Patent B2
US 10,243,056 · App. 15/479,459 · Granted Mar 26, 2019

Semiconductor device and method for fabricating the same

Inventors: Hyun Kwan Yu (Suwon-si, KR); Kyung Ho Kim (Seoul, KR); Dong Suk Shin (Yongin-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L29/4983H01L21/823418H01L21/823431H01L21/823468H01L21/823878H01L27/0886H01L27/1104H01L29/0649H01L29/0847H01L29/161H01L29/165H01L29/1608H01L29/66545H01L29/785H01L29/7848H01L21/823814H01L21/823821H01L21/823864H01L27/0924
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Quick Facts
Patent No.
US 10,243,056
App. No.
15/479,459
Granted
Mar 26, 2019
Kind
B2
Abstract

A semiconductor device includes a field insulating film including a first region and a second region on a substrate, a recess in the first region of the field insulating film, a gate electrode on the second region of the field insulating film, and a gate spacer along a sidewall of the gate electrode and a sidewall of the recess.

Claims (22)

1. A semiconductor device, comprising:

a field insulating film including a first region and a second region on a substrate;

a recess in the first region of the field insulating film;

a gate electrode on the second region of the field insulating film; and

a gate spacer along a sidewall of the gate electrode and a sidewall of the recess.

2. The semiconductor device as claimed in claim 1 , wherein the gate spacer includes:

an inner spacer and an outer spacer sequentially stacked on the sidewall of the gate electrode.

3. The semiconductor device as claimed in claim 2 , wherein a distance from an upper surface of the gate electrode to an upper surface of the second region of the field insulating film is less than a distance from the upper surface of the gate electrode to a lowermost portion of the outer spacer.

4. The semiconductor device as claimed in claim 2 , wherein:

the inner spacer has an L-shape, and

the outer spacer has an I-shape.

5. The semiconductor device as claimed in claim 1 , further comprising:

a semiconductor pattern on the first region of the field insulating film,

wherein a distance from an upper surface of the gate electrode to a bottom surface of the semiconductor pattern is less than a distance from the upper surface of the gate electrode to an upper surface of the second region of the field insulating film.

6. The semiconductor device as claimed in claim 5 , further comprising:

an air gap between the semiconductor pattern and the field insulating film.

7. The semiconductor device as claimed in claim 1 , further comprising:

a trench defined by the gate spacer, on the second region of the field insulating film; and

a high dielectric gate insulating film extending along a sidewall and a bottom surface of the trench.

8. The semiconductor device as claimed in claim 1 , further comprising:

an insulating pattern protruding from the gate spacer, on the first region of the field insulating film, wherein the insulating pattern is substantially parallel to an upper surface of the second region of the field insulating film.

9. The semiconductor device as claimed in claim 1 , wherein a first distance from an upper surface of the gate electrode to an upper surface of the second region of the field insulating film is less than a second distance from the upper surface of the gate electrode to a lowermost portion of the gate spacer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2017
From: YU, HYUN KWAN; KIM, KYUNG HO; SHIN, DONG SUK
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 041855/0760 →
Priority Claims (1)
KR 10-2016-0067531 · May 31, 2016 · national
Continuity (1)
Related Publication 20170345911A1 · Nov 30, 2017