Method of uniform channel formation
Embodiments described herein generally provide a method and apparatus to form semiconductor devices. Specifically, embodiments describe an apparatus and methods of forming channels in sub-5 nm node FinFETS. The method provides for various processing steps to deposit a dielectric layer over a substrate. The method continues by etching a trench in the dielectric layer, depositing a silicon layer within the trench, depositing a buffer layer on top of the silicon layer in the trench, removing a portion of the buffer layer to form a planar surface, etching the buffer layer into a v-shape, and depositing a channel layer on top of the v-shaped buffer layer. The v-shaped buffer layer advantageously negates facet formation and provides for an InGaAs fin-channel with uniform distribution of indium and gallium throughout the channel.
1. A method of channel formation, comprising:
depositing a dielectric material on a substrate;
etching the dielectric material to form a trench;
depositing a silicon material in the trench;
overfilling the trench with a buffer material;
planarizing the buffer material to remove the overfill;
etching the buffer material to form a v-shaped trench; and
depositing a channel material in the v-shaped trench.
2. The method of claim 1 , wherein the etching the dielectric material to form the trench exposes a portion of the substrate and wherein the silicon material is deposited on the exposed portion of the substrate.
3. The method of claim 1 , further comprising etching the dielectric material to expose the channel material.
4. The method of claim 1 , wherein the buffer material is a type III-V semiconductor material.
5. The method of claim 4 , wherein the buffer material is selected from the group consisting of gallium arsenide and indium phosphide.
6. The method of claim 1 , wherein the dielectric material is selected from the group consisting of silicon oxide, silicon nitride, and aluminum oxide.
7. The method of claim 1 , wherein the channel material is selected from the group consisting of indium phosphide, indium aluminum arsenide, and indium gallium arsenide.
8. The method of claim 1 , wherein the channel material has a thickness in a range from about 10 nanometers to about 60 nanometers.
9. A method of channel formation, comprising:
depositing a dielectric material on a substrate;
etching the dielectric material to form a trench;
depositing a silicon material into the trench;
etching the silicon material in the trench into a v-shape;
depositing a buffer material on top of the v-shaped silicon material in the trench;
removing a portion of the buffer material to form a planar surface;
etching the buffer material into a v-shape; and
depositing a channel material on top of the v-shaped buffer material.
10. The method of claim 9 wherein the etching the dielectric material to form the trench exposes a portion of the substrate.
11. The method of claim 9 , wherein the buffer material is a type III-V semiconductor.
12. The method of claim 11 , wherein the buffer material is selected from the group consisting of gallium arsenide and indium phosphide.
13. The method of claim 9 , wherein the dielectric material is selected from the group consisting of type III-V semiconductors, silicon oxide, silicon nitride, and aluminum oxide.
14. The method of claim 9 , wherein the channel material is selected from the group consisting of indium phosphide, indium aluminum arsenide, and indium gallium arsenide.
15. The method of claim 9 , wherein the channel material has a thickness in a range from about 10 nanometers to about 60 nanometers.