IP Library › Granted Patent US 10,248,000
Granted Patent B2
US 10,248,000 · App. 15/914,826 · Granted Apr 2, 2019

Semiconductor optical element and method for manufacturing the same

Inventors: Takamitsu Kitamura (Yokohama, JP); Masataka Watanabe (Yokohama, JP)
Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
G02F1/2257G02F1/025H01L21/76826H01L21/76829H01L24/05H01L24/45H01L24/48H01L24/85H01S5/0265H01S5/0425H01S5/12H01S5/227
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Quick Facts
Patent No.
US 10,248,000
App. No.
15/914,826
Granted
Apr 2, 2019
Kind
B2
Abstract

A semiconductor optical element is disclosed. The semiconductor optical element includes: a mesa-shaped optical waveguide formed on a substrate; a modulation electrode formed on the optical waveguide; a first resin layer that buries side surfaces of the optical waveguide; a bonding pad formed on the first resin layer; and a connecting wiring line that connects the modulation electrode and the bonding pad. In the semiconductor optical element, side surfaces of the bonding pad are partially covered with a second resin layer provided on the first resin layer, and the connecting wiring line extends on the second resin layer.

Claims (33)

1. A semiconductor optical element, comprising:

a mesa-shaped optical waveguide formed on a substrate;

a modulation electrode formed on the optical waveguide;

a first resin layer that buries side surfaces of the optical waveguide;

a bonding pad formed on the first resin layer; and

a connecting wiring line that connects the modulation electrode and the bonding pad, wherein

side surfaces of the bonding pad are partially covered with a second resin layer provided on the first resin layer, and

the connecting wiring line extends on the second resin layer.

2. The semiconductor optical element of claim 1 , wherein

the bonding pad has a structure in which an upper region is stacked on an upper surface of a lower region,

in a stacking plane between the lower region and the upper region, a width of the upper region is smaller than a width of the lower region, and

a region where the upper region is not provided on the upper surface of the lower region is covered with the second resin layer.

3. The semiconductor optical element of claim 1 , wherein a thickness of the upper region is greater than a thickness of the second resin layer.

4. The semiconductor optical element of claim 1 further comprising

a first inorganic film between the first resin layer and the bonding pad.

5. The semiconductor optical element of claim 4 , further comprising:

a second inorganic film, provided on the second resin layer; and

a third inorganic film provided on the second inorganic film, wherein

the bonding pad extends to an upper surface of the second resin layer, and

a rim of a portion of the bonding pad is vertically interposed between the second inorganic film and the third inorganic film, the portion of the bonding pad extending the upper surface of the second resin layer.

6. The semiconductor optical element of claim 1 , wherein the first resin layer is harder than the second resin layer.

7. The semiconductor optical element of claim 1 , further comprising a semiconductor structure having a semiconductor stack structure that is the same as a semiconductor stack structure of the mesa-shaped optical waveguide,

wherein the semiconductor structure is provided on the substrate at a portion between a side surface of the semiconductor optical element and the bonding pad.

8. A semiconductor optical element manufacturing method, comprising the steps of:

burying side surfaces of a mesa-shaped optical waveguide with a first resin layer, the mesa-shaped optical waveguide being provided on a substrate;

forming a modulation electrode on the optical waveguide;

forming a bonding pad on the first resin layer;

forming a second resin layer on the first resin layer; and

forming a connecting wiring line that connects the modulation electrode and the bonding pad, and extends on the second resin layer,

wherein, when the second resin layer is formed, side surfaces of the bonding pad are partially covered with the second resin layer.

9. The semiconductor optical element manufacturing method of claim 8 , wherein

the step of burying the side surfaces with the first resin layer includes subjecting the first resin layer to thermal hardening treatment, and

the step of forming the second resin layer includes subjecting the second resin layer to thermal hardening treatment.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2018
From: KITAMURA, TAKAMITSU; WATANABE, MASATAKA
To: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Reel/Frame 045137/0722 →
Priority Claims (1)
JP 2017-058070 · Mar 23, 2017 · national
Continuity (1)
Related Publication 20180275482A1 · Sep 27, 2018