The invention provides a GOA circuit, comprising a plurality of GOA units, for a positive integer n, n-th GOA unit comprising: a first TFT (T 1 ), a second TFT (T 2 ), a third TFT (T 3 ), a fourth TFT T( 4 ), a fifth TFT (T 5 ), a sixth TFT (T 6 ), a seventh TFT (T 7 ), an eighth TFT (T 8 ), a ninth TFT (T 9 ), a tenth TFT (T 10 ), a first capacitor (C 1 ) and a second capacitor (T 2 ). The invention, based on known GOA circuit, uses T 9 and T 10 so as to achieve forward and backward scanning without D2U and U2D control signals, which facilitates narrow border design and simplifies corresponding driving timing and reduce IC cost.
1. A gate driver on array (GOA) circuit, comprising a plurality of cascade GOA units, for a positive integer n, the n-th GOA unit comprising:
a first thin film transistor (TFT), a gate of the first TFT connected to a constant high voltage, a first source/drain of the first transistor is directly connected to an signal output node of (n−2)th GOA unit, a second source/drain of the first transistor is directly connected to a first source/drain of a ninth TFT;
a ninth TFT, a gate of the ninth TFT connected to the signal output node of the (n−2)th GOA unit, and a second source/drain of the ninth transistor is directly connected to a third node;
a third TFT, a gate of the third TFT connected to the constant high voltage, a first source/drain of the third transistor is directly connected to an signal output node of (n+2)th GOA unit, a second source/drain of the third transistor is directly connected to a first source/drain of a tenth TFT;
a tenth TFT, a gate of the tenth TFT connected to the signal output node of the (n+2)th GOA unit, and a second source/drain of the tenth transistor is directly connected to the third node;
a seventh TFT, a gate of the seventh TFT connected to the third node, a source and a drain of the seventh transistor are directly connected respectively to a second node and a constant low voltage;
a sixth TFT, a gate of the sixth TFT connected to the second node, a source and a drain of the sixth transistor are directly connected respectively to the third node and the constant low voltage;
a fifth TFT, a gate of the fifth TFT connected to the constant high voltage, a source and a drain of the fifth transistor are directly connected respectively to the third node and the first node;
an eighth TFT, a gate of the eighth TFT inputted a second clock signal, a source and a drain of the eighth transistor are directly connected respectively to the second node and the constant high voltage;
a second TFT, a gate of the second TFT connected to the first node, a source and a drain of the second transistor are directly connected respectively to the signal output node of n-th GOA unit and an first clock signal;
a first capacitor, having the two ends connected respectively to the first node and the signal output node of n-th GOA unit;
a fourth TFT, a gate of the fourth TFT connected to the second node, a source and a drain of the fourth transistor are directly connected respectively to the signal output node of n-th GOA unit and the constant low voltage;
a second capacitor, having the two ends connected respectively to the second node and the constant low voltage.
2. The GOA circuit as claimed in claim 1 , wherein the first clock signal and the second clock signal are rectangular waves having a duty ratio of 0.25, and the waveforms between the first clock signal and the second clock signal differ by a half cycle.
3. The GOA circuit as claimed in claim 1 , wherein for the first GOA unit in the cascade, when starting forward scanning, the signal output node of (n−2)th GOA unit inputs the high voltage signal as an activation signal.
4. The GOA circuit as claimed in claim 1 , wherein for the second GOA unit in the cascade, when starting forward scanning, the signal output node of (n−2)th GOA unit inputs the high voltage signal as an activation signal.
5. The GOA circuit as claimed in claim 1 , wherein for the last GOA unit in the cascade, when starting backward scanning, the signal output node of (n+2)th GOA unit inputs the high voltage signal as an activation signal.
6. The GOA circuit as claimed in claim 1 , wherein for the second last GOA unit in the cascade, when starting backward scanning, the signal output node of (n+2)th GOA unit inputs the high voltage signal as an activation signal.
7. The GOA circuit as claimed in claim 1 , wherein the GOA circuit is for low temperature polysilicon (LPTS) panel.
8. The GOA circuit as claimed in claim 1 , wherein the GOA circuit is for organic light-emitting diode (OLED) panel.
9. A gate driver on array (GOA) circuit comprising: a plurality of cascade GOA units, for a positive integer n, the n-th GOA unit comprising:
a first thin film transistor (TFT), a gate of the first TFT connected to a constant high voltage, a first source/drain of the first transistor is directly connected to an signal output node of (n−2)th GOA unit, a second source/drain of the first transistor is directly connected to a first source/drain of a ninth TFT;
a ninth TFT, a gate of the ninth TFT connected to the signal output node of the (n−2)th GOA unit, and a second source/drain of the ninth transistor is directly connected to a third node;
a third TFT, a gate of the third TFT connected to the constant high voltage, a first source/drain of the third transistor is directly connected to an signal output node of (n+2)th GOA unit, a second source/drain of the first third is directly connected to a first source/drain of a tenth TFT;
a tenth TFT, a gate of the tenth TFT connected to the signal output node of the (n+2)th GOA unit, and a second source/drain of the tenth transistor is directly connected to the third node;
a seventh TFT, a gate of the seventh TFT connected to the third node, a source and a drain of the seventh transistor are directly connected respectively to a second node and a constant low voltage;
a sixth TFT, a gate of the sixth TFT connected to the second node, a source and a drain of the sixth transistor are directly connected respectively to the third node and the constant low voltage;
a fifth TFT, a gate of the fifth TFT connected to the constant high voltage, a source and a drain of the fifth transistor are directly connected respectively to the third node and the first node;
an eighth TFT, a gate of the eighth TFT inputted a second clock signal, a source and a drain of the eighth transistor are directly connected respectively to the second node and the constant high voltage;
a second TFT, a gate of the second TFT connected to the first node, a source and a drain of the second transistor are directly connected respectively to the signal output node of n-th GOA unit and an input first clock signal;
a first capacitor, having the two ends connected respectively to the first node and the signal output node of n-th GOA unit;
a fourth TFT, a gate of the fourth TFT connected to the second node, a source and a drain of the fourth transistor are directly connected respectively to the signal output node of n-th GOA unit and the constant low voltage;
a second capacitor, having the two ends connected respectively to the second node and the constant low voltage;
wherein the first clock signal and the second clock signal being rectangular waves having a duty ratio of 0.25, and the waveforms between the first clock signal and the second clock signal differing by a half cycle;
wherein for the first GOA unit in the cascade, when starting forward scanning, the signal output node of (n−2)th GOA unit inputting the high voltage signal as an activation signal.
10. The GOA circuit as claimed in claim 9 , wherein for the second GOA unit in the cascade, when starting forward scanning, the signal output node of (n−2)th GOA unit inputs the high voltage signal as an activation signal.
11. The GOA circuit as claimed in claim 9 , wherein for the last GOA unit in the cascade, when starting backward scanning, the signal output node of (n+2)th GOA unit inputs the high voltage signal as an activation signal.
12. The GOA circuit as claimed in claim 9 , wherein for the second last GOA unit in the cascade, when starting backward scanning, the signal output node of (n+2)th GOA unit inputs the high voltage signal as an activation signal.
13. The GOA circuit as claimed in claim 9 , wherein the GOA circuit is for low temperature polysilicon (LPTS) panel.
14. The GOA circuit as claimed in claim 9 , wherein the GOA circuit is for organic light-emitting diode (OLED) panel.