Device for avoiding hard switching in resonant converter and related method

1. A method, comprising:

precharging a bootstrap capacitor of a resonant converter for a first time period during an initial switching cycle of the resonant converter;

maintaining a high-side transistor and a low-side transistor in a half-bridge circuit of the resonant converter switched off for a second time period after the first time period during the initial switching cycle, a half-bridge node being defined at an interconnection of the high-side and low-side transistors and each of the high-side and low-side transistors including a body diode and the second time period being long enough to allow any oscillations of a half-bridge voltage on the half-bridge node to reduce to a level that will not cause current to flow through the body diodes of the high-side and low-side transistors; and

switching on the high-side transistor after expiration of the second time period during the initial switching cycle.

2. The method of claim 1 , wherein precharging the bootstrap capacitor comprises turning on the low-side transistor for the first time period.

3. The method of claim 1 further comprising turning the high-side and low-side transistors on and off without relation to the first and second time periods during switching cycles after the initial switching cycle.

4. The method of claim 1 , wherein the second time period starts upon termination of the first time period.

5. The method of claim 1 , wherein a voltage across the bootstrap capacitor is used to turn on the high-side transistor and wherein the second time period is short enough to prevent the bootstrap capacitor from being discharged to reduce the voltage across the bootstrap capacitor to a level that will not allow proper turning on of the high-side transistor.

6. The method of claim 5 , wherein the second time period is equal to five times the first time period.

7. A circuit, comprising:

a timer circuit configured to generate a first control signal defining a first time period and a second control signal defining a second time period; and

a controller configured to control a high-side and a low-side transistor in response to the first and second control signals, a common node being defined between the high-side and low-side transistors and each of the high-side and low-side transistors having a body diode, the controller configured to turn on the low-side transistor for the first time period and configured to turn off the high-side and the low-side transistors for the second time period to allow any oscillations on the common node to diminish to a level that does not cause current to flow through the body diodes.

8. The circuit of claim 7 , wherein the second time period immediately follows the first time period and the second time period has a longer duration than the first time period.

9. The circuit of claim 8 , wherein the second time period is equal to five times the first time period.

10. The circuit of claim 7 , wherein the controller is configured to turn on the low-side transistor for the first time period to precharge the bootstrap capacitor to a level sufficient to properly turn on the high-side transistor.

11. The circuit of claim 7 , wherein the controller is configured to control the high-side and low-side transistors in response to the first and second control signals only during a first switching cycle of the half-bridge circuit.

12. The circuit of claim 7 , wherein the controller is further configured to control the turning on and off of the high-side and low-side transistors without relation to the first and second time periods during switching cycles after the first switching cycle.

13. The circuit of claim 7 , wherein the timer circuit comprises a first timer configured to time the first time period and a second timer configured to time the second time period.

14. The circuit of claim 13 , wherein the first timer circuit includes a first capacitor that is charged to time the first time period and the second timer circuit includes a second capacitor that is charged to time the second time period.

15. The circuit of claim 14 , wherein first timer circuit is configured to generate a stop signal in response to a voltage across the first capacitor reaching a first threshold and wherein the second timer circuit is configured to start charging the second capacitor in response to the stop signal.

16. A switching converter, comprising:

a switching circuit including a half-bridge circuit having a high-side and a low-side switch coupled to each other at an intermediate node;

a bootstrap capacitor coupled to the intermediate node; and

a control circuit that in operation controls the switching circuit, the control circuit including:

a timer circuit that in operation generates a first control signal defining a first time period and a second control signal defining a second time period; and

a controller that in operation controls the high-side and a low-side switches in response to the first and second control signals, and that in operation turn on the low-side switches for the first time period and turns off the low-side and the high-side switches for the second time period to allow any oscillations on the intermediate node to diminish to a desired level, and that in operation controls the high-side and low-side switches independent of the first and second control signals during switching cycles subsequent to the initial switching cycle.

17. The switching converter of claim 16 , where each of the high-side and low-side switches comprises a MOSFET.

18. The switching converter of claim 16 , wherein the switching converter comprises an LLC type resonant converter.

19. The switching converter of claim 16 , wherein the switching converter comprises a DC-DC resonant converter.