IP Library › Granted Patent US 10,256,228
Granted Patent B2
US 10,256,228 · App. 15/858,242 · Granted Apr 9, 2019

Semiconductor device

Inventors: Yoshihito Uzawa (Tokyo, JP); Yasuyuki Morishita (Tokyo, JP); Masanori Tanaka (Tokyo, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H01L27/027H01L27/0255H01L27/0277H01L27/0288H01L27/0629
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Quick Facts
Patent No.
US 10,256,228
App. No.
15/858,242
Granted
Apr 9, 2019
Kind
B2
Abstract

A semiconductor device includes a MOS transistor which is coupled between two terminals and discharges current which flows caused by generation of static electricity and a diode which is coupled between a back gate of the MOS transistor and one of the terminal and has a polarity which is reversed to the polarity of a parasitic diode which is formed between the back gate and a source of the MOS transistor.

Claims (51)

1. A semiconductor device, comprising:

first and second terminals which serve as external terminals of a semiconductor chip;

an electrostatic destruction protection transistor whose source is coupled to the first terminal and whose drain is coupled to the second terminal;

a diode which is coupled between a back gate of the electrostatic destruction protection transistor and the first terminal; and

an RC circuit coupled to the first and second terminals, the RC circuit comprising a resistor and a capacitor,

wherein one of the resistor and the capacitor is located between a gate of the electrostatic destruction protection transistor and a first wiring that couples the diode to the first terminal, and another one of the resistor and the capacitor is located between the gate of the electrostatic destruction protection transistor and a second wiring that couples the back gate of the electrostatic destruction protection transistor to the second terminal, and

wherein the diode is arranged such that a polarity thereof which occurs in a coupling direction is reversed to a polarity of a parasitic diode which is formed between the back gate and the source of the electrostatic destruction protection transistor.

2. The semiconductor device according to claim 1 ,

wherein the resistor is coupled to the first terminal at one end and is coupled to the gate and the back gate of the electrostatic destruction protection transistor at an other end,

wherein the capacitor is coupled to the gate of the electrostatic destruction protection transistor at one end and is coupled to the second terminal at an other end, and

wherein the resistor is coupled in parallel with the diode.

3. The semiconductor device according to claim 1 ,

wherein the capacitor is coupled to the first terminal at one end,

wherein the resistor is coupled to the second terminal at one end and is coupled to an other end of the capacitor at an other end,

the semiconductor device further comprising:

a first inverter whose input terminal is coupled to a third wiring which couples together the capacitor and the resistor and whose output terminal is coupled to the gate of the electrostatic destruction protection transistor; and

a second inverter whose input terminal is coupled to the third wiring which couples together the capacitor and the resistor and whose output terminal is coupled to the back gate of the electrostatic destruction protection transistor.

4. The semiconductor device according to claim 1 , wherein the electrostatic destruction protection transistor comprises an N-type MOS transistor,

wherein the first terminal comprises a grounding terminal, and

wherein the second terminal comprises a power source terminal.

5. The semiconductor device according to claim 1 , wherein the electrostatic destruction protection transistor comprises a P-type MOS transistor,

wherein the first terminal comprises a power source terminal, and

wherein the second terminal comprises a grounding terminal.

6. The semiconductor device according to claim 1 , wherein the electrostatic destruction protection transistor comprises an N-type output MOS transistor,

wherein the first terminal comprises a grounding terminal, and

wherein the second terminal comprises an output terminal,

the semiconductor device further comprising:

a resistor which is coupled in parallel with the diode.

7. The semiconductor device according to claim 1 , wherein the electrostatic destruction protection transistor comprises a P-type output MOS transistor,

wherein the first terminal comprises a power source terminal, and

wherein the second terminal comprises an output terminal,

the semiconductor device further comprising:

a resistor which is coupled in parallel with the diode.

8. The semiconductor device according to claim 1 , wherein opposing ends of the RC circuit are directly connected to the first and second terminals, respectively.

9. The semiconductor device according to claim 8 , wherein the electrostatic destruction protection transistor is directly connected to the first and second terminals.

10. The semiconductor device according to claim 9 , wherein the source of the electrostatic destruction protection transistor is directly connected to the first terminal.

11. The semiconductor device according to claim 10 , wherein the second wiring directly connects the drain of the electrostatic destruction protection transistor to the second terminal.

12. The semiconductor device according to claim 11 , wherein the resistor and the capacitor are disposed on opposing sides of a node that connects the gate of the electrostatic destruction protection transistor to the RC circuit.

13. The semiconductor device according to claim 12 , wherein the node is placed adjacent to the gate of the electrostatic destruction protection transistor and between the resistor and the capacitor.

14. The semiconductor device according to claim 1 , wherein the electrostatic destruction protection transistor is directly connected to the first and second terminals.

15. The semiconductor device according to claim 1 , wherein the source of the electrostatic destruction protection transistor is directly connected to the first terminal.

16. The semiconductor device according to claim 1 , wherein the second wiring directly connects the drain of the electrostatic destruction protection transistor to the second terminal.

17. The semiconductor device according to claim 1 , wherein the resistor and the capacitor are disposed on opposing sides of a node that connects the gate of the electrostatic destruction protection transistor to the RC circuit.

18. The semiconductor device according to claim 17 , wherein the node is placed adjacent to the gate of the electrostatic destruction protection transistor and between the resistor and the capacitor.

19. A semiconductor device, comprising:

first and second terminals;

an electrostatic destruction protection transistor coupled to the first and second terminals;

a diode which is coupled between a back gate of the electrostatic destruction protection transistor and the first terminal; and

an RC circuit coupled to the first and second terminals, the RC circuit comprising a resistor and a capacitor,

wherein one of the resistor and the capacitor is located between a gate of the electrostatic destruction protection transistor and a first wiring that couples the diode to the first terminal, and another one of the resistor and the capacitor is located between the gate of the electrostatic destruction protection transistor and a second wiring that couples the back gate of the electrostatic destruction protection transistor to the second terminal.

20. The semiconductor device according to claim 19 , wherein a polarity of the diode which occurs in a coupling direction is reversed to a polarity of a parasitic diode which is formed between the back gate and the source of the electrostatic destruction protection transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2018
From: UZAWA, YOSHIHITO; MORISHITA, YASUYUKI; TANAKA, MASANORI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044539/0114 →
Priority Claims (1)
JP 2017-011250 · Jan 25, 2017 · national
Continuity (1)
Related Publication 20180211949A1 · Jul 26, 2018
Cited By (1)
US 12,394,759