Three dimensional semiconductor memory device
A three-dimensional semiconductor memory device is provided. A stacked structure is formed on a substrate. The stacked structure includes conductive patterns vertically stacked on the substrate. A selection structure including selection conductive patterns is stacked on the stacked structure. A channel structure penetrates the selection structure and the stacked structure to connect to the substrate. An upper interconnection line crosses the selection structure. A conductive pad is disposed on the channel structure to electrically connect the upper interconnection line to the channel structure. A bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the selection conductive patterns.
1. A three-dimensional semiconductor memory device, comprising:
a stacked structure including a plurality of conductive patterns vertically stacked on a substrate;
a selection structure including first, second, and third selection conductive patterns sequentially stacked on the stacked structure;
a channel structure penetrating the selection structure and the stacked structure to connect to the substrate;
an upper interconnection line crossing the selection structure; and
a conductive pad disposed on the channel structure to electrically connect the upper interconnection line to the channel structure,
wherein a bottom surface of the conductive pad is positioned between top and bottom surfaces of the third selection conductive pattern,
wherein the conductive pad has impurities of a first conductivity type, and the channel structure comprises a channel impurity region having impurities of a second conductivity type different from the first conductivity type and positioned adjacent to the first and second selection conductive patterns, and
wherein the channel impurity region is spaced apart from the bottom surface of the conductive pad.
2. The device of claim 1 , wherein the bottom surface of the conductive pad is positioned between top surfaces of two adjacent selection conductive patterns in a vertical direction.
3. The device of claim 1 , wherein the bottom surface of the conductive pad is positioned between top and bottom surfaces of the uppermost selection conductive pattern.
4. The device of claim 1 , wherein a thickness of the conductive pad is greater than that of the uppermost selection conductive pattern.
5. The device of claim 1 , wherein the plurality of selection conductive patterns is electrically connected to each other to be in an equipotential state.
6. The device of claim 1 , wherein
the first selection conductive pattern is electrically separated from the second selection conductive patterns.
7. The device of claim 1 , further comprising:
a vertical insulating layer vertically extending from a region between the channel structure and the stacked structure to a region between the channel structure and the selection structure; and
a horizontal insulating layer provided between the vertical insulating layer and the channel structure and extended to cover top and bottom surfaces of the selection conductive patterns and the conductive patterns.
8. The device of claim 1 , wherein a vertical insulating layer vertically extends from a region between the channel structure and the selection structure to cover a sidewall of the conductive pad.
9. The device of claim 1 , wherein at least one of the plurality of selection conductive patterns has substantially the same thickness as that of at least one of the plurality of conductive patterns.
10. The device of claim 1 , wherein the first, second, and third selection conductive patterns are electrically connected in common.
11. A three-dimensional semiconductor memory device, comprising:
a substrate;
a vertical channel formed on the substrate;
a conductive pad formed on the vertical channel, wherein the conductive pad includes impurities of a first conductivity type;
a bit line formed on the conductive pad, wherein the bit line is electrically coupled to the conductive pad;
a plurality of word lines vertically formed on the substrate which is adjacent to the vertical channel; and
first, second, and third selection conductive patterns sequentially stacked on the plurality of word lines,
wherein the vertical channel includes a channel impurity region and an offset region, wherein the offset region is interposed between the conductive pad and the channel impurity region, and wherein the channel impurity region has impurities of a second conductivity type different from the first conductivity type,
wherein the channel impurity region is adjacent the first and second selection conductive patterns, and
wherein an impurity concentration of the channel impurity region is maximum at a position between the first and the second selection conductive patterns.
12. The three-dimensional semiconductor memory device of claim 11 , wherein the bottom surface of the conductive pad is positioned between top and bottom surfaces of the third selection conductive pattern.
13. The three-dimensional semiconductor memory device of claim 11 , wherein the third selection conductive pattern horizontally overlap the conductive pad, and the remaining selection conductive patterns horizontally overlap the channel impurity region.
14. The three-dimensional semiconductor memory device of claim 11 , wherein the first conductivity type is of n-type, and the second conductivity type is of p-type.
15. The three-dimensional semiconductor memory device of claim 11 , wherein the offset region, the conductive pad and the third selection conductive pattern constitutes a selection transistor, wherein the offset region serves as a source/drain of the selection transistor.