SOI island in a power semiconductor device
A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device. The insulation structure includes a sidewall that laterally confines the semiconductor region; a bottom that vertically confines the semiconductor region; and a local deepening that forms at least a part of a transition between the sidewall and the bottom, wherein the local deepening extends further along the extension direction as compared to the bottom.
1. A method of producing a semiconductor-on-insulator island in a power semiconductor device, the method comprising:
providing a semiconductor body with a plurality of trenches, each trench including an insulator, wherein the plurality of trenches includes first trenches designated for a pattern-collapse processing step and a border trench arranged adjacent to at least one of the first trenches, the border trench having a first sidewall facing the at least one first trench and an opposite second sidewall;
providing a mask having an opening exposing a first section that comprises each of the first sidewall of the border trench and the first trenches, and wherein the mask covers a second section including at least the second sidewall of the border trench;
removing the insulator included in the first section being exposed by the opening; and
subjecting the first section to the pattern-collapse-processing step while maintaining the insulator at the second sidewall of the border trench, thereby transforming the first trenches into at least one buried cavity.
2. The method of claim 1 , wherein the pattern-collapse-processing step comprises a tempering step in an atmosphere including hydrogen at a portion of at least 30% while maintaining the insulator at the second sidewall.
3. The method of claim 1 , wherein during the pattern-collapse-processing step, the first section borders the insulator present in the border trench.
4. The method of claim 1 , wherein during the pattern-collapse-processing step, at a transition between a termination of the insulator present in the border trench and the semiconductor body, a part of each of the insulator and the semiconductor body is transformed into a volatile material.
5. The method of claim 1 , further comprising, after the pattern-collapse-processing step:
removing the insulator in the second section that has been covered by the mask.
6. The method of claim 1 , further comprising, after the pattern-collapse-processing step:
carrying out an oxidation processing step to create an insulation structure having an oxide at each of the second sidewall and at the at least one buried cavity.
7. The method of claim 6 , wherein the oxidation processing step includes a thermal oxidation to grow the oxide.
8. The method of claim 6 , wherein the oxide forms a contiguous insulation structure having a bottom and at least one sidewall, the sidewall of the contiguous insulation structure being formed by the oxide that has been created at the second sidewall of the border trench.
9. The method of claim 8 , wherein the contiguous insulation structure separates a semiconductor region from a remaining portion of the semiconductor body.
10. The method of claim 9 , further comprising providing a periphery circuitry in the semiconductor region.
11. The method of claim 6 , wherein the oxidation processing step is carried out without a mask.
12. The method of claim 6 , wherein the second sidewall provides at least for a part of an atmospheric connection to the at least one buried cavity during the oxidation processing step.
13. The method of claim 1 , wherein at least one of the first trenches interfaces with the border trench.
14. The method of claim 1 , wherein the border trench surrounds the first trenches.