Low-inductance half-bridge arrangement
The switching performance of a half-bridge arrangement particularly for a converter shall be improved. For this purpose, a half-bridge arrangement has a circuit board having at least four trace layers and two switching elements and a capacitor device arranged on opposite sides of the circuit board and interconnected so as to produce, during a commutation event of the half-bridge arrangement, at least two dipoles having opposite spatial directions.
1. A half-bridge arrangement for a converter, comprising
two switching elements connected in series at a node,
an intermediate circuit capacitor device comprising two capacitors,
a circuit board on which the switching elements and the capacitor device are arranged and interconnected to form a half bridge, the circuit board having two major surfaces and at least four trace layers which interconnect the switching elements and the intermediate circuit capacitor device such that, during a commutation event of the half-bridge, at least two magnetic dipoles having opposite spatial directions are produced by current flow in and between the at least four trace layers, and
wherein the two capacitors are disposed in a point-symmetric fashion on different major surfaces of the circuit board.
2. The half-bridge arrangement of claim 1 , wherein the two switching elements and the two capacitors are each disposed on different major surfaces of the circuit board.
3. The half-bridge arrangement of claim 1 , wherein the circuit board has four trace layers which form at least four parallel commutation circuits during the commutation event.
4. The half-bridge arrangement of claim 3 , wherein the at least four parallel commutation circuits are formed symmetric with respect to one another.
5. The half-bridge arrangement of claim 1 , wherein the node occupies a surface area on the circuit board that is significantly smaller than the surface area of the circuit board so as to increase interference immunity of the half-bridge arrangement.
6. The half-bridge arrangement of claim 5 , wherein the surface area occupied by the node is smaller than approximately 5% of the surface area of the circuit board.
7. The half-bridge arrangement of claim 1 , wherein the at least four circuit trace layers have a highest possible copper fill factor.
8. The half-bridge arrangement of claim 1 , wherein a copper fill factor of the at least four circuit trace layers is optimized for heat dissipation.
9. A half-bridge arrangement for a converter, comprising
two switching elements connected in series at a node,
an intermediate circuit capacitor device,
a circuit board on which the switching elements and the capacitor device are arranged and interconnected to form a half bridge, the circuit board having two major surfaces and at least four trace layers which interconnect the switching elements and the intermediate circuit capacitor device such that, during a commutation event of the half-bridge, at least two magnetic dipoles having opposite spatial directions are produced by current flow in and between the at least four trace layers, and
driver devices connected to control terminals of the switching devices in one-to-one correspondence such that a driver current direction of a main current of a driver device is orthogonal to a commutation current direction of the main current for that driver device during the commutation event.
10. The half-bridge arrangement of claim 9 , wherein the circuit board has four trace layers which form at least four parallel commutation circuits during the commutation event.
11. A converter comprising:
a half-bridge arrangement with
two switching elements connected in series at a node,
an intermediate circuit capacitor device comprising two capacitors,
a circuit board on which the switching elements and the capacitor device are arranged and interconnected to form a half bridge, the circuit board having two major surfaces and at least four trace layers which interconnect the switching elements and the intermediate circuit capacitor device such that, during a commutation event of the half-bridge, at least two magnetic dipoles having opposite spatial directions are produced by current flow in and between the at least four trace layers, and
wherein the two capacitors are disposed in a point-symmetric fashion on different major surfaces of the circuit board.
12. The half-bridge arrangement of claim 11 , wherein the at least four parallel commutation circuits are formed symmetric with respect to one another.