Cascode switch circuit including level shifter
Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.
1. A cascode switch circuit comprising:
a normally-on transistor connected to a drain terminal;
a normally-off transistor connected to a source terminal, the normally-off transistor being connected to the normally-on transistor in cascade form;
a level shifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the normally-on transistor, the level shifter being connected between the gate terminal and a first resistor; and
a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the normally-off transistor, the buffer being connected between the gate terminal and the gate of the normally-off transistor
wherein the first resistor is connected between the level shifter and the gate of the normally-on transistor.
2. The cascode switch circuit of claim 1 , wherein a drain of the normally-on transistor is connected to the drain terminal, a source of the normally-off transistor is connected to the source terminal, and a source of the normally-on transistor and a drain of the normally-off transistor are connected to each other.
3. The cascode switch circuit of claim 1 , wherein the level shifter sets a voltage between the gate and source of the normally-on transistor to about 0 V or greater.
4. The cascode switch circuit of claim 1 , wherein the buffer delays the switching control signal by a changing time of the level shifter.
5. The cascode switch circuit of claim 4 , wherein the buffer further delays the switching control signal by a delay time due to the first resistor.
6. The cascode switch circuit of claim 5 , wherein the delay time of the buffer may be adjusted in an analog manner or a digital manner.
7. The cascode switch circuit of claim 1 , wherein a magnitude of the first resistor is set such that a switching transition time of the normally-on transistor coincides with a switching transition time of the normally-off transistor.
8. The cascode switch circuit of claim 7 , wherein the first resistor is a variable resistor.
9. The cascode switch circuit of claim 1 , further comprising:
at least one first transistor identical to the normally-on transistor and connected to the normally-on transistor in parallel; and
at least one second transistor identical to the normally-off transistor and connected to the normally-off transistor in parallel.
10. The cascode switch circuit of claim 1 , further comprising:
a first clamp circuit configured to limit a voltage level between the gate and a source of the normally-on transistor; and
a second clamp circuit configured to limit a voltage level between the gate and a source of the normally-off transistor.
11. The cascode switch circuit of claim 10 , wherein the first clamp circuit comprises:
a second resistor connected to the gate of the normally-on transistor;
a first zener diode comprising a first anode and a first cathode, the first anode being connected to the second resistor; and
a second zener diode comprising a second anode and a second cathode, the second anode being connected to the source of the normally-on transistor and the second cathode being connected to the first cathode, and
the second clamp circuit comprises:
a third resistor connected to the gate of the normally-off transistor;
a third zener diode comprising a third anode and a third cathode, the third anode being connected to the third resistor; and
a fourth zener diode comprising a fourth anode and a fourth cathode, the fourth anode being connected to the source of the normally-off transistor and the fourth cathode being connected to the third cathode.
12. The cascode switch circuit of claim 10 , further comprising:
at least one first transistor identical to the normally-on transistor and connected to the normally-on transistor in parallel; and
at least one second transistor identical to the normally-off transistor and connected to the normally-off transistor in parallel.
13. The cascode switch circuit of claim 12 , further comprising:
at least one third clamp circuit configured to limit a voltage level between a gate and a source of the at least one third transistor; and
at least one fourth clamp circuit configured to limit a voltage level between a gate and a source of the at least one fourth transistor.
14. The cascode switch circuit of claim 1 , wherein the normally-on transistor comprises gallium nitride (GaN) or silicon carbide (SiC), and the normally-off transistor comprises silicon (Si).