IP Library Granted Patent US 10,256,813
Granted Patent B2
US 10,256,813 · App. 15/497,337 · Granted Apr 9, 2019

Fast transient high-side gate driving circuit

Inventors: Taewoo Kwak (San Diego, CA); Joseph Rutkowski (Chandler, AZ)
Assignee: QUALCOMM Incorporated
H03K17/6872H02M3/158H02M1/08
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Quick Facts
Patent No.
US 10,256,813
App. No.
15/497,337
Granted
Apr 9, 2019
Kind
B2
Abstract

Techniques for improving the transient response in a switching converter are provided. An example of a gate driving circuit for driving a high-side switch in a switching converter according to the disclosure includes a first switch operably coupled to a source lead and a gate lead of the high-side switch, a first super source follower circuit operably coupled to the gate lead of the high-side switch, and a mid-voltage power supply operably coupled to the first super source follower circuit.

Claims (40)

1. A gate driving circuit for driving a high-side switch in a switching converter, comprising:

a first switch operably coupled to a source lead and a gate lead of the high-side switch;

a first super source follower circuit operably coupled to the gate lead of the high-side switch, wherein the first super source follower circuit includes at least a p-channel semiconductor switch, a n-channel semiconductor switch and a resistor; and

a mid-voltage power supply operably coupled to the first super source follower circuit.

2. The gate driving circuit of claim 1 wherein the high-side switch is a p-channel semiconductor switch.

3. The gate driving circuit of claim 2 wherein the high-side switch is a p-type field-effect transistor (PFET).

4. The gate driving circuit of claim 1 wherein the p-channel semiconductor switch is a p-type field-effect transistor (PFET) and the n-channel semiconductor switch is a n-type field-effect transistor (NFET).

5. The gate driving circuit of claim 4 wherein a source of the PFET is operably coupled to the gate lead of the high-side switch, and a drain lead of the PFET is operably coupled to a gate lead of the NFET and the resistor.

6. The gate driving circuit of claim 5 wherein the mid-voltage power supply is operably coupled to a gate of the PFET.

7. The gate driving circuit of claim 1 wherein the switching converter is configured to output a desired output voltage and a voltage output of the mid-voltage power supply is greater than a difference between the desired output voltage and a gate-to-source voltage rating for the high-side switch.

8. The gate driving circuit of claim 1 further comprising at least a second super source follower circuit operably coupled between the first super source follower circuit and the mid-voltage power supply.

9. The gate driving circuit of claim 8 further comprising at least a third super source follower circuit operably coupled between the second super source follower circuit and the mid-voltage power supply.

10. A method of constructing a switched-mode power converter, comprising:

configuring the switched-mode power converter including at least a high-side switch and a low-side switch based on a desired output voltage;

operably coupling a gate driving circuit to the high-side switch, wherein the gate driving circuit includes a first switch and a first super source follower circuit;

operably coupling a mid-voltage power supply to the first super source follower circuit, wherein a mid-voltage power supply voltage is based on the desired output voltage and a gate-to-source voltage rating of the high-side switch; and

operably coupling a second super source follower circuit between the first super source follower circuit and the mid-voltage power supply.

11. The method of claim 10 wherein the desired output voltage is greater than the gate-to-source voltage rating for the high-side switch.

12. The method of claim 10 wherein the first super source follower circuit includes at least a p-type field-effect transistor (PFET), a n-type field-effect transistor (NFET), and a resistor, and operably coupling the gate driving circuit to the high-side switch includes connecting a source lead of the PFET and a drain lead of the NFET to a gate lead on the high-side switch.

13. The method of claim 12 wherein operably coupling the mid-voltage power supply to the first super source follower circuit includes operably coupling the mid-voltage power supply to a gate lead on the PFET.

14. The method of claim 10 wherein the mid-voltage power supply voltage is greater than a difference between the desired output voltage and the gate-to-source voltage rating of the high-side switch.

15. A gate driving circuit, comprising:

a power stage switch including a gate-source voltage rating and a drain-source voltage rating, wherein the gate-source voltage rating is lower than the drain-source voltage rating;

a first super source follower circuit operably coupled to a gate lead of the power stage switch, wherein the first super source follower circuit includes at least a p-channel semiconductor switch, a n-channel semiconductor switch and a resistor; and

a mid-voltage power supply operably coupled to the first super source follower circuit.

16. The gate driving circuit of claim 15 wherein the power stage switch is an n-channel semiconductor switch.

17. The gate driving circuit of claim 15 wherein the power stage switch is a p-type field-effect transistor (PFET).

18. The gate driving circuit of claim 15 wherein the p-channel semiconductor switch is a p-type field-effect transistor (PFET) and the n-channel semiconductor switch is a n-type field-effect transistor (NFET).

19. The gate driving circuit of claim 18 wherein the mid-voltage power supply is operably coupled to a gate of the PFET.

20. The gate driving circuit of claim 15 further comprising at least a second super source follower circuit operably coupled between the first super source follower circuit and the mid-voltage power supply.

21. The gate driving circuit of claim 20 further comprising at least a third super source follower circuit operably coupled between the second super source follower circuit and the mid-voltage power supply.

22. An apparatus, comprising:

a power converter means including a power stage switch;

a gate driving means operably coupled to the power stage switch, wherein the gate driving means includes a first super source follower circuit; and

a mid-voltage power means operably coupled to the first super source follower circuit, and

a second super source follower circuit operably coupled between the first super source follower circuit and the mid-voltage power means.

23. The apparatus of claim 22 wherein the power stage switch includes a gate-source voltage rating and a drain-source voltage rating, and the gate-source voltage rating is less than the drain-source voltage rating.

24. The apparatus of claim 23 wherein an output voltage from the power converter means is greater than the gate-source voltage rating.

25. The apparatus of claim 24 wherein the mid-voltage power means provides a mid-voltage value that is greater than a difference between the output voltage and the gate-source voltage rating.

26. The apparatus of claim 22 wherein the first super source follower circuit includes at least a p-type field-effect transistor (PFET), a n-type field-effect transistor (NFET), and a resistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2017
From: KWAK, TAEWOO; RUTKOWSKI, JOSEPH
To: QUALCOMM INCORPORATED
Reel/Frame 042416/0782 →
Continuity (1)
Related Publication 20180316345A1 · Nov 1, 2018