Memristive dot product engine for vector processing

1. A memristive dot product system for vector processing, comprising:

a crossbar array having a number of memory elements, each memory element comprising a memristor and a transistor in series with one another;

a vector input register; and

a vector output register.

2. The system of claim 1 , in which the crossbar array comprises N rows, M columns and N×M memory elements.

3. The system of claim 2 , in which the input register comprises N voltage inputs to the crossbar array and the output register receives M voltage outputs from the crossbar array.

4. The system of claim 2 , in which the N×M memory elements correspond with values contained in an N×M matrix.

5. The system of claim 1 , further comprising a normally ON depletion mode transistor at each memory element.

6. The memristive dot product system of claim 1 , wherein the memristor of each memory element has a plurality of conductance levels greater than two.

7. The memristive dot product system of claim 6 , wherein the transistor of each memory element has a plurality of different gate voltages corresponding to the conductance levels.

8. The memristive dot product system of claim 7 , wherein the memristor of each memory element is programmable via a plurality of different current levels controlled by the different gate voltages of the transistor of the memory element.

9. A memristive dot-product engine for vector processing, comprising:

a crossbar array comprising a number of memory locations, each memory location comprising a memory element to store information corresponding to a value contained in an N×M matrix and a transistor to control current flow through the memory element, an end of the memory element connected to an end of the transistor such that no electrical component is connected at a location between the end of the memory element and the end of the transistor;

an input register comprising N voltage inputs, each voltage input corresponding to a value contained in a vector having N values; and

an output register comprising M voltage outputs.

10. The dot-product engine of claim 9 , wherein the transistors are normally ON transistors.

11. The dot-product engine of claim 10 , further comprising M bias voltage wires, in which a jth wire (j=1,M) is connected to the gates of the normally ON transistors comprising a jth column of memory locations.

12. The dot-product engine of claim 11 , in which the normally ON transistors are depletion mode transistors.

13. The dot-product engine of claim 11 , in which the memory elements comprising a jth column of memory locations are linear memristors.

14. A method for vector-processing using a memristive dot product engine, comprising:

providing a crossbar array comprising M columns, N rows and N×M memory locations, each memory location comprising a memristor and a transistor, an input register comprising N voltage inputs, and an output register comprising M voltage outputs, the memristor and the transistor in series with one another with no electrical component connected at a location between the memristor and the transistor;

setting memristance values at the N×M memory locations within the crossbar array, the memristance values corresponding to row and column values of an N×M matrix, wherein the memristance value at memory location Ni,Mj is set by applying a programming voltage across the memristor at memory location Ni,Mj;

setting input voltages at the N voltage inputs, the input voltages corresponding to values of an Nx1 vector to be multiplied with the N×M matrix;

determining output voltages at the M voltage outputs, each output voltage corresponding to the current output at each of the M columns of the crossbar array; and

representing the Mx1 vector result of the multiplication of the N×M matrix and the Nx1 vector.

15. The method of claim 14 , wherein the M voltage outputs are determined by passing current outputs at each of the M columns of the crossbar array through a resistance device.

16. The method of claim 14 , wherein the series of steps of setting memristance values at the N×M memory locations within the crossbar array, setting input voltages at the N voltage inputs, and determining output voltages at the M voltage outputs is performed iteratively until a convergence criteria is satisfied.

17. The method of claim 14 , wherein each memory element further comprises a transistor to switch on and off current flow through the memristor.

18. The method of claim 14 , wherein the transistor at a memory location Ni,Mj is a normally ON depletion mode transistor.