IP Library › Granted Patent US 10,262,930
Granted Patent B2
US 10,262,930 · App. 15/492,291 · Granted Apr 16, 2019

Interposer and method for manufacturing interposer

Inventor: Kazuki Kajihara (Ogaki, JP)
Assignee: IBIDEN CO., LTD.
H01L23/49822H01L21/4857H01L23/293H01L23/3128H01L23/49816H01L23/49827H01L23/49838H01L23/49894H01L24/09H01L24/17H01L24/49H01L25/105H01L25/50H01L23/13H01L23/49833H01L24/48H01L2224/0401H01L2224/04042H01L2224/48091H01L2225/1023H01L2225/1058H01L2225/1094
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Quick Facts
Patent No.
US 10,262,930
App. No.
15/492,291
Granted
Apr 16, 2019
Kind
B2
Abstract

An interposer includes an insulating layer, conductor circuits formed in grooves formed on a first surface of the insulating layer respectively, and metal posts formed in openings extending from the grooves to a second surface of the insulating layer on the opposite side with respect to the first surface such that the metal posts are connected to the conductor circuits respectively. The insulating layer has an opening portion which accommodates an electronic component and is extending from the first surface to the second surface of the insulating layer, and each of the metal posts has an upper surface and a bottom surface on the opposite side of the upper surface such that the upper surface is connected to a respective one of the conductor circuits and that the bottom surface is exposed from the second surface of the insulating layer.

Claims (34)

1. A semiconductor device, comprising:

a printed wiring board;

a semiconductor element mounted on the printed wiring board;

an interposer laminated on the printed wiring board such that the semiconductor element is accommodated in an opening portion of the interposer; and

a mold resin structure formed between the interposer and the semiconductor element in the opening portion of the interposer,

wherein the mold resin structure and an insulating layer of the interposer are formed such that a thermal expansion coefficient of the mold resin structure and a thermal expansion coefficient of the insulating layer are equal to each other, the interposer comprises the insulating layer, a plurality of conductor circuits formed in a plurality of grooves formed on a first surface of the insulating layer respectively, and a plurality of metal posts formed in a plurality of openings extending from the grooves to a second surface of the insulating layer on an opposite side with respect to the first surface such that the metal posts are connected to the conductor circuits respectively, the insulating layer has the opening portion configured to accommodate the semiconductor element and extending from the first surface to the second surface of the insulating layer, and each of the metal posts has an upper surface and a bottom surface on an opposite side of the upper surface such that the upper surface is connected to a respective one of the conductor circuits and that the bottom surface is exposed from the second surface of the insulating layer.

2. The semiconductor device according to claim 1 , wherein the insulating layer comprises an inorganic filler and a resin material comprising an epoxy resin.

3. The semiconductor device according to claim 2 , wherein the insulating layer is formed such that the opening portion is positioned in a central portion of the insulating layer.

4. The semiconductor device according to claim 3 , further comprising:

a second printed wiring board mounted on the interposer such that the second printed wiring board is positioned on an opposite side of the interposer with respect to the printed wiring board.

5. The semiconductor device according to claim 1 , further comprising:

a second printed wiring board mounted on the interposer such that the second printed wiring board is positioned on an opposite side of the interposer with respect to the printed wiring board.

6. The semiconductor device according to claim 5 , further comprising:

a second semiconductor element mounted on the second printed wiring board.

7. The semiconductor device according to claim 6 , wherein the printed wiring board is connected to the interposer through a plurality of first solder balls on the second surface of the insulating layer at the plurality of metal posts, and the second printed wiring board is connected to the interposer through a plurality of second solder balls on the first surface of the insulating layer at the plurality of conductor circuits.

8. The semiconductor device according to claim 7 , wherein the semiconductor element is an IC chip, and the second semiconductor element is a memory.

9. The semiconductor device according to claim 6 , wherein the semiconductor element is an IC chip, and the second semiconductor element is a memory.

10. The semiconductor device according to claim 5 , wherein the printed wiring board is connected to the interposer through a plurality of first solder balls on the second surface of the insulating layer at the plurality of metal posts, and the second printed wiring board is connected to the interposer through a plurality of second solder balls on the first surface of the insulating layer at the plurality of conductor circuits.

11. The semiconductor device according to claim 2 , further comprising:

a second printed wiring board mounted on the interposer such that the second printed wiring board is positioned on an opposite side of the interposer with respect to the printed wiring board.

12. The semiconductor device according to claim 11 , further comprising:

a second semiconductor element mounted on the second printed wiring board.

13. The semiconductor device according to claim 1 , wherein the insulating layer comprises the inorganic filler in an amount in a range of 75 wt % to 85 wt %.

14. The semiconductor device according to claim 13 , wherein the insulating layer is formed such that the opening portion is positioned in a central portion of the insulating layer.

15. The semiconductor device according to claim 13 , further comprising:

a second printed wiring board mounted on the interposer such that the second printed wiring board is positioned on an opposite side of the interposer with respect to the printed wiring board.

16. The semiconductor device according to claim 15 , further comprising:

a second semiconductor element mounted on the second printed wiring board.

17. The semiconductor device according to claim 1 , wherein the insulating layer is formed such that the opening portion is positioned in a central portion of the insulating layer.

18. The semiconductor device according to claim 17 , further comprising:

a second printed wiring board mounted on the interposer such that the second printed wiring board is positioned on an opposite side of the interposer with respect to the printed wiring board.

19. The semiconductor device according to claim 18 , further comprising:

a second semiconductor element mounted on the second printed wiring board.

20. The semiconductor device according to claim 1 , wherein the printed wiring board is connected to the interposer through a plurality of first solder balls on the second surface of the insulating layer at the plurality of metal posts.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2017
From: KAJIHARA, KAZUKI
To: IBIDEN CO., LTD.
Reel/Frame 042271/0636 →
Priority Claims (1)
JP 2016-084133 · Apr 20, 2016 · national
Continuity (1)
Related Publication 20170309558A1 · Oct 26, 2017