FinFET LDMOS devices with additional dynamic control
View Patent ↗A FinFET semiconductor device having semiconductor body including a source region of a first type, and a drain region of a second type, and a drain-region shallow trench isolation (STI) disposed in the drain region. The device includes a plurality of fins attached to the semiconductor body and extending across the semiconductor body, a channel gate disposed over a section of the plurality of fins; a supplemental gate disposed on the drain-region STI.
1. A FinFET semiconductor device comprising:
a semiconductor body including a source region of a first type, and a drain region of a second type, and a drain-region shallow trench isolation (STI) disposed in the drain region;
a plurality of fins attached to the semiconductor body and extending across the semiconductor body;
a channel gate structure disposed over a section of said plurality of fins;
a supplemental gate disposed on the drain-region STI.
2. The device of claim 1 , wherein the plurality of fins comprises an undoped semiconductor material.
3. The device of claim 2 , wherein the plurality of fins comprises undoped silicon, and the semiconductor body comprises at least doped silicon for the source region and the drain region.
4. The device of claim 1 , wherein the drain-region STI extends to a depth of 60 nm.
5. The device of claim 4 , wherein the supplemental gate, when biased, accumulates charge in a region of the semiconductor body proximate the drain-region STI.
6. The device of claim 4 , wherein the supplemental gate, when biased, depletes charge from a region of the semiconductor body proximate the drain-region STI.
7. The device of claim 1 , wherein the drain-region STI and the supplemental gate are offset from an end of the plurality of fins opposite the source region by 2-50 nm.
8. The device of claim 1 , wherein the drain-region STI and the supplemental gate are offset from an end of the plurality of fins opposite the source region by 5-10 nm.
9. The device of claim 1 , wherein an edge of the drain-region STI is aligned an end of the plurality of fins opposite the source region.
10. The device of claim 8 , further comprising peripheral shallow trench isolations isolating the source and drain regions from device components outside of the peripheral shallow trench isolations.
11. The device of claim 1 , wherein at least one of the source and drain regions comprises a raised contact.
12. The device of claim 1 , wherein the drain region comprises a raised drain contact disposed an opposite side of the drain-region STI from the plurality of fins.
13. The device of claim 1 , further comprising a pseudo drain contact disposed between the drain-region STI and the plurality of fins.
14. The device of claim 1 , wherein the source region comprises an epitaxial doped region adjoining the plurality of fins.
15. The device of claim 1 , wherein the supplemental gate comprises two supplemental control gates disposed on the drain-region STI.
16. The device of claim 1 , wherein said semiconductor body, the plurality of fins, and the supplemental gate comprise an n-channel metal-oxide-semiconductor (NMOS) device.
17. The device of claim 1 , wherein said semiconductor body, the plurality of fins, and the supplemental gate comprise a p-channel metal-oxide-semiconductor (PMOS) device.
18. The device of claim 1 , wherein said semiconductor body, the plurality of fins, and the supplemental gate comprise a depletion mode metal-oxide-semiconductor (MOS) device.