Semiconductor device and manufacturing method thereof

1. A semiconductor device, comprising:

a first semiconductor layer;

a second semiconductor layer spaced apart from the first semiconductor layer and disposed on the first semiconductor layer;

a gate stack structure disposed on the second semiconductor layer;

a third semiconductor layer positioned between the first and second semiconductor layers; and

a channel pillar passing through the gate stack structure, the second semiconductor layer and the third semiconductor layer and extending into the first semiconductor layer;

wherein the third semiconductor layer is in contact with the channel pillar, and

wherein the third semiconductor layer includes a first protrusion protruding in an interface between the second semiconductor layer and the channel pillar.

2. The semiconductor device of claim 1 , further comprising a first multilayer memory pattern surrounding the channel pillar, the first multilayer memory pattern having a bottom surface which is in contact with a top surface of the first protrusion of the third semiconductor layer.

3. The semiconductor device of claim 2 , wherein the bottom surface of the first multilayer memory pattern is flat or horizontal.

4. The semiconductor device of claim 2 , wherein the bottom surface of the first multilayer memory pattern has a negative slope in a direction from a sidewall of the channel pillar toward the gate stack structure.

5. The semiconductor device of claim 2 , wherein the bottom surface of the first multilayer memory pattern has a convex polygonal line shape or a convex shape in a direction from the gate stack structure toward the first semiconductor layer.

6. The semiconductor device of claim 2 , wherein the bottom surface of the first multilayer memory pattern is disposed between a first level and a second level, the first level being spaced by 100 Å from an interface between the gate stack structure and the second semiconductor layer toward the gate structure, the second level being spaced by 20 Å from the interface between the gate stack structure and the second semiconductor layer toward the first semiconductor layer.

7. The semiconductor device of claim 2 , wherein the bottom surface of the first multilayer memory pattern is disposed between a first level and a second level, the first level being spaced by 50 Å from an interface between the gate stack structure and the second semiconductor layer toward the gate structure, the second level being spaced by 20 Å from the interface between the gate stack structure and the second semiconductor layer toward the first semiconductor layer.

8. The semiconductor device of claim 2 , wherein the first multilayer memory pattern includes a tunnel insulating layer, a data storage layer and a blocking insulating layer stacked in a sequential manner from the channel pillar toward the gate stack structure.

9. The semiconductor device of claim 1 , wherein each of the first and third semiconductor layers includes a p-type dopant.

10. The semiconductor device of claim 1 , wherein the second semiconductor layer is an undoped semiconductor layer, or includes a p-type dopant.

11. The semiconductor device of claim 1 , further comprising:

a spacer insulating layer extending along sidewalls of the gate stack structure, the second semiconductor layer, and the third semiconductor layer; and

a source contact layer formed on the spacer insulating layer and contacting the first semiconductor layer.

12. The semiconductor device of claim 11 , further comprising a source junction defined in the first to third semiconductor layers and disposed adjacent to the spacer insulating layer and the source contact layer.

13. The semiconductor device of claim 12 , wherein each of the first and third semiconductor layers includes a dopant of a first conductivity type, and

the source junction includes a dopant of a second conductivity type different from the first conductivity type.

14. The semiconductor device of claim 12 , wherein the source junction includes an n-type dopant.

15. The semiconductor device of claim 12 , wherein the source junction comprises:

a first region including a dopant of a second conductivity type at a first concentration; and

a second region including the dopant of the second conductivity type at a second concentration greater than the first concentration.

16. The semiconductor device of claim 15 , wherein the second region is defined in the first semiconductor layer to contact the source contact layer, and

the first region is defined in the first semiconductor layer adjacent to a sidewall of the second region and in the second and third semiconductor layers adjacent to a sidewall of the source contact layer.

17. The semiconductor device of claim 1 , wherein the gate stack structure comprises:

a gate insulating layer contacting the second semiconductor layer; and

conductive patterns and interlayer insulating layers stacked alternately on the gate insulating layer,

wherein the gate insulating layer has a smaller thickness than the interlayer insulating layers.

18. The semiconductor device of claim 1 , wherein the third semiconductor layer further comprises:

a second protrusion protruding between the first semiconductor layer and the channel pillar; and

a second multilayer memory pattern disposed between the first semiconductor layer and the channel pillar to surround the channel pillar.